Research

Supervisor:	Mr. Anthony Fong
Research Field:	Computer Architecture and VLSI Design
Research Topic:	High-level Instruction Set Computer (HISC)

Introduction to HISC

Due to the demands on faster and more powerful computers, the computer architectures are pushed into evolutions to fit the demands. Since the concept of CISC (Complex Instruction Set Computer) reached to a point that complex instructions will lead to harder design of a good compiler and the use of microcoding techniques can hardly boost the performance of the computer anymore, a new type of computer architecture -- RISC (Reduced Instruction Set Computer), became popular.

The design of RISC used large register file, super-scalar, super-pipelining, caching and branch prediction techniques to boost the performance of computing, but it is now reaches to a point that many additional introductions of implementing different techniques can achieve only very little improvements in performance. So to boost the performance of RISC further, the clock rate of the processor was increased, but now the clock rate of the state-of-the-art processors go beyond 400 MHz, and further increasing on clock rate will be very difficult since the limit of silicon will soon be reached. A reasonable way to further boost the computing speed to to do more work in a cycle, but RISC cannot achieve that with its simple instruction set.

So a new architecture -- HISC was proposed by Mr. Anthony Fong to handle those problems. Unlike the HLLM (High-Level Language Machine) which is language dependent and VLIW (Very Long Instruction Word) architecture which is implementation and resource dependent, HISC is a general purpose architecture which aims for high performance, implementation flexibility, expandability, better access control and system dependent features for nowadays demands in high computing power and multimedia applications.

HISC is a 64-bit architecture which involves simple instructions of fixed length, entries of operand descriptors and application oriented data types. The operands of an instruction are described by Operand Descriptors which is records which consist of virtual addresses, data types, operand sizes, vector information, operand access codes and design and system dependent information for the operand. The data types of the operands include integer, floating-point number, BCD, character and string. The vector information include number of elements in the vector and element spacing for vector operands.

HISC reduced the demands in conditional branching as in RISC by eliminates the looping counts for operands of variable lengths and large size, as well as vectors. On the other hand, HISC will operate super-scalar in a higher level. The inter-dependency of operands will be much less, while it is much likely to operate super-scalar for two or more function units. HISC also keep the vector information so that vector operations will be done by hardware.

The greatest deficiency of HISC is that it need to access the operand descriptors, and the limited number of operand specifiers, which can be solved by a good operand descriptor cache and extension of the length of operand descriptor pointer respectively.

Publications

1. Architecture Support of Protection on a Descriptor Computer HISC [postscript format]
2. Architecture Support of a Descriptor Computer on Object-Orientation [postscript format]

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