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Stencil Printing for Enhanced SMT and Wafer Level Bumping

Abstract

In this presentation, the basics of stencil printing will be explained. In particular the different kinds of stencils will be explained as well as their limitations and capabilities. Market studies on stencil printing will also be offered. The different applications of stencil printing will be given with an emphasis of wafer level bumping. A new class of stencils will be presented that permits a cost reduction for wafer level bumping compared to electroplating or sputtering. This new market will allow packaging companies to leap frog their competitors and place them at a competitive advantage.

Speaker Biographical Sketch

Dr Marc Desmulliez was born in France in 1963 and graduated from the Grande Ecole "Ecole Superieure d'Electricite of Paris, France" in 1987. He completed two Masters of Science at University College London (1987) and the University of Cambridge (1991) in modern optics and theoretical physics respectively. He also has a Ph.D. from Heriot Watt University, Edinburgh, UK (1995) in optoelectronics. Dr Desmulliez co-ordinates the activities in MEMS (microsystems engineering) at Heriot-Watt University with a staff of 6 academics, and 20 Ph.D.s and Research Associates. Recently and in collaboration with the University of Greenwich, Dr Desmulliez invented a new manufacturing process for the stencil print of less than 100 microns pitch deposits of lead free solder and ICAs. The work culminated in a spin out company MicroStencil Ltd (http://www.microstencil.com) that commercialises the products. Dr Desmulliez is a member of the IEE, a Certified Physicist and Chartered Engineer. He holds two patents and has published over 100 articles.

Date: 4 November 2005 (Friday)
Time: 2:30pm – 4:30pm
Venue: Rm B6605, 6/F, Lift 7, Academic Bldg, City University of Hong Kong,
83 Tat Chee Avenue, Kowloon Tong, Kowloon,
Hong Kong.
Language: English

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