ARC 2012 (19 - 23 March 2012)
Preliminary
Technical Programme
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Monday 19
March 2012 |
0830-1800
Registration
0900-1800
Xilinx Education Workshop Day 1 - City University of Hong Kong
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1800 End of Workshop Day 1 |
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Tuesday 20
March 2012 |
0830-1800
Registration
0900-1800
Xilinx Education Workshop Day 2 - City University of Hong Kong
0900-1800
Altera Education Workshop - The Chinese University of Hong Kong
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1830-2030 Welcome Reception - 9/F, CityTop, City University of Hong Kong |
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1800 End of Workshop Day 2 |
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Wednesday 21
March 2012 |
0800-1800
Registration
0830-0900
Welcome Address
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0900-0945 Keynote 1: Prof. Michael J. Flynn, Stanford
University, USA Title:
Maximizing application speedup using reconfigurable data flow machines |
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0945-1000 Coffee Break & Questions |
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Session 1: Design Methods and Tools I Chair: Kentaro Sano |
1000-1025
Paper : Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration
Authors : Karel Heyse, Brahim Al Farisi, Karel Bruneel and Dirk Stroobandt
1025-1050
Paper : Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
Authors : Kizheppatt Vipin and Suhaib A Fahmy
1050-1115
Paper : Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array
Authors : Wang Luzhou, Kentaro Sano and Satoru Yamamoto
1115-1140
Paper : Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture
Authors : Yongjoo Kim, Jongeun Lee, Toan X. Mai, Jinyong Lee, Ingoo Heo and Yunheung Paek
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1140-1300 Lunch |
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1300-1345 Keynote 2: Prof. Dr.-Ing. Sorin A. Huss, Technische Universitaet Darmstadt, Germany Title: Novel
reconfigurable TPM architectures as the security anchors of future embedded
IT systems |
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1345-1400 Coffee Break & Questions |
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Session 2: Applications I Chair: Peter Athanas |
1400-1425
Paper
: Multi-level Customisation Framework for
Curve Based Monte Carlo Financial Simulations
Authors : Qiwei
Jin, David Thomas, Diwei Dong, Wayne Luk, Anson H.T. Tse, Gary C.T.
Chow and Stephen Weston
1425-1450
Paper
: Optimising Performance of Quadrature Methods
with Reduced Precision
Authors : Anson H.T. Tse,
Gary C.T. Chow, Qiwei Jin, David Thomas and Wayne Luk
1450-1515
Paper
: Cost Effective Implementation of Flux Limiter Functions using Partial
Reconfiguration
Authors : Mohamad
Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
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1515-1600 Coffee Break and Poster Session 1 |
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Session 3: Architectures I Chair: Suhaib Fahmy |
1600-1625
Paper
: PPMC : A Programmable Pattern based Memory
Controller
Authors : Tassadaq
Hussain, Muhammad Shafiq, Miquel Pericas, Eduard Ayguade and Nacho Navarro
1625-1650
Paper
: A Run-time Task Migration Scheme for an Adjustable Issue-slots
Multi-core Processor
Authors : Fakhar
Anjam, Quan Kong, Roel Seedorf and Stephan Wong
1650-1715
Paper
: Boosting Single Thread Performance in Mobile Processors via Recongurable Acceleration
Authors : Geoffrey Ndu
1715-1740
Paper
: Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs
Authors : Gang Zhou, Li Li and Harald Michalik
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1740 – 1745 End of Conference Day 1 |
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Thursday 22 March
2012 |
0830-1300
Registration
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0900-0945 Keynote 3: Prof. Cetin Kaya Koc, University of California, Santa Barbara, USA Title:
Security Analysis of 3-D Integrated Crypto Co-processors |
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0945-1000 Coffee Break & Questions |
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Session 4: Critical Issues Chair: Ray Cheung |
1000-1025
Paper
: Teaching Hardware/Software Codesign on a
Reconfigurable Computing Platform
Authors : Markus Weinhardt
1025-1050
Paper
: Securely Sealing Multi-FPGA Systems
Authors : Tim Guneysu,
Igor L. Markov and Andre Weimerskirch
1050-1115
Paper
: FPGA Paranoia: Testing numerical properties of FPGA floating point
IP-cores
Authors : Xuan
You Tan, David Boland and George Constantinides
1115-1140
Paper
: High Performance Reconfigurable Architecture for Double Precision
Floating Point Division
Authors : Manish Kumar Jaiswal and Ray C.C. Cheung
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1140-1330 Lunch and Poster Session 2 |
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1330 – 1700 Conference Tour |
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1700 - 2100 Conference Dinner (Hong Kong Tour) Ying Chinese Cuisine, (1/Floor, Fu Ho Building, 3-7 Kau Yuk Road, Yuen Long) |
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1800 - 1900 Keynote 4: Prof. Wayne Luk, Imperial College London, UK Title:
Efficiency and productivity challenges in reconfigurable computing |
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2100 – 2115 End of Conference Day 2 |
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Friday 23 March
2012 |
0830-1800
Registration
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0900-0945 Keynote 5: Mr. Grant Martin, Chief Scientist, Tensilica Inc., USA Title:
"ARC for Better Living": The future of (re-)configurable
technology |
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0945-1000 Coffee Break & Questions |
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Session 5: Architectures II Chair: Erkay Savas |
1000-1025
Paper
: ScalableCore System: A Scalable Many-core
Simulator by Employing Over 100 FPGAs
Authors : Shinya Takamaeda-Yamazaki,
Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda and
Kenji Kise
1025-1050
Paper
: Scalable Memory Hierarchies for Embedded Manycore
Systems
Authors : Sen
Ma, Miaoqing Huang, Eugene Cartwright and David
Andrews
1050-1115
Paper
: Triple module redundancy of a laser array driver circuit for optically
reconfigurable gate arrays
Authors : Takahiro Watanabe and Minoru
Watanabe
1115-1140
Paper
: A Routing Architecture for FPGAs with Dual-VT Switch Boxes and Logic
Clusters
Authors : Wei Ting Loke
and Yajun Ha
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1140-1300 Lunch |
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Session 6: Design Methods and Tools II Chair: Hayden So |
1300-1325
Paper : Table-based division by small integer constants
Authors : Florent De Dinechin and Laurent-Stephane Didier
1325-1350
Paper : Heterogeneous Systems for Energy Efficient Scientific Computing
Authors : Qiang Liu and Wayne Luk
1350-1415
Paper : The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
Authors : S. Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi and Koen Bertels
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1415-1445 Coffee Break |
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Session 7: Applications II Chair: Evan Young |
1445-1510
Paper
: Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware
Authors : Grigorios
Mingas and Christos-Savvas Bouganis
1510-1535
Paper
: A High Throughput FPGA-based Impelementation
of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
Authors : Abid Rafique, Nachiket Kapre and George A. Constantinides
1535-1600
Paper
: A Low-Cost and High-Performance Virus Scanning Engine Using a Binary
CAM Emulator and an MPU
Authors : Hiroki Nakahara, Tsutomu Sasao and Munehiro Matsuura
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1600-1615 Closing Remarks |
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1615 End of Conference Day 3 |
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POSTER
SESSION 1 Paper : A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems Authors : Tannous Frangieh, Richard Stroop, Peter Athanas and Teresa Cervero Paper
: Constructing Cluster of Simple FPGA boards for Cryptologic
Computations Authors : Yarkin Doroz and Erkay Savas Paper
: Reconfigurable Multicore Architecture for Dynamic Processor
Reallocation Authors : Annie
Avakian, Natwar Agrawal and Ranga Vemuri Paper
: Efficient Multi-Node Communication for FPGA Clusters Authors : Stewart
Denholm, Kuen Hung Tsoi and Wayne Luk Paper
: Performance Analysis of Reconfigurable Processors Using MVA Analysis Authors : Ehsan Zadkhosh, Sepide Fatahi and Mahmood Ahmadi |
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POSTER
SESSION 2 Paper
: PDPR: Fine-grained Placement for Dynamic Partially Reconfigurable
FPGAs Authors : Ruining
He, Guoqiang Liang, Yuchun
Ma, Yu Wang and Jinian Bian Paper
: A Connection Router for the Dynamic Reconfiguration of FPGAs Authors : Elias
Vansteenkiste, Karel Bruneel and Dirk Stroobandt Paper
: R-NoC: an Efficient Packet-Switched
Reconfigurable Networks-on-Chip Authors : Hongbing Fan and Yu-Liang Wu Paper
: Novel Arithmetic Architecture for High Performance Implementation of
SHA-3 Finalist Keccak on FPGA Platforms Authors : Kashif Latif, M Muzaffar Rao, Athar Mahboob and Arshad Aziz Paper
: CRAIS: A Crossbar based Adaptive Interconnection Scheme Authors : Chao
Wang, Xi Li, Xiaojing Feng
and Xuehai Zhou |