Previous ARC Workshops
Honorary Keynote Speakers
Prof. Michael J. Flynn
Professor, IEEE Fellow, ACM Fellow
Department of Electrical Engineering
Topic: Maximizing application speedup using reconfigurable data flow machines
For many high performance computing applications the alternative to the
standard multicore nodes is to create processing nodes with integrated
accelerators. At Maxeler we've found that the customized data flow machine
technology provides the maximum performance for many applications. The
application data flow graph is transformed into a data centric graph and then
implemented as an optimized static data flow machine using FPGAs. The
application is configured as a streaming computation, using a synchronous data
flow activated by data streams, realizing a pipeline of up to 500 stages.
Given the initial area-time-power disadvantage of the FPGA compared to (say) a
custom designed adder this is a surprising result. The sheer magnitude of the
available FPGA parallelism overcomes the initial disadvantage. As an example we
consider modeling problems in geophysics. In a typical problem we realize a
2000 node array on 2 FPGA's, with a resulting 50- 100 times speedup over a
conventional multicore server.
Michael Flynn received his Ph.D. from Purdue University in 1961. He joined IBM
in 1955 and for ten years worked in the areas of computer organization and
design. He was design manager of prototype versions of the IBM 7090 and
7094/II, and later for the System 360 Model 91 Central Processing Unit. Between
1966 and 1974 Prof. Flynn was a faculty member of Northwestern University and
the Johns Hopkins University. In 1975 he became Professor of Electrical
Engineering at Stanford University, and was Director of the Computer Systems
Laboratory from 1977 to 1983. He was founding chairman of both the ACM Special
Interest Group on Computer Architecture and the IEEE Computer Society's
Technical Committee on Computer Architecture. Prof. Flynn was the 1992
recipient of the ACM/IEEE Eckert-Mauchley Award for his technical contributions
to computer and digital systems architecture. He was the 1995 recipient of the
IEEE-CS Harry Goode Memorial Award in recognition of his outstanding
contribution to the design and classification of computer architecture. In 1998
he received the Tesla Medal from the International Tesla Society (Belgrade),
and an honorary Doctor of Science from Trinity College (University of Dublin),
Ireland. He is the author of three books and over 250 technical papers.
Prof. Dr.-Ing. Sorin A. Huss
Integrated Circuits and Systems Lab (ICS)
Departments of Computer Science and of Electrical Engineering
Technische Universitaet Darmstadt, Germany
Topic: Novel reconfigurable TPM architectures as the security anchors of future embedded IT systems
With the emergence of new technologies the requirements for trusted platforms are constantly changing. Thus, the current Trusted Platform Modules (TPMs) have to cope with issues they have not been designed for. One such deficit of current TPMs is the inability to support multiple stakeholders as required in mobile computing, virtualization, and cloud computing applications. In such scenarios, a TPM has to attest the state of their applications on the platform to all involved stakeholders and to additionally protect their individual assets. On the other hand, embedded system implementations are increasingly exploiting reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). Due to the volatile natureof SRAM-based FPGAs it is necessary to secure such systems against intellectual property theft. Additionally, the trustworthy operation of these systems has to be guarded in order to protect the processed data.
In this contribution we present novel reconfigurable TPM architectures, which address the security requirements of a wide range of IT systems. At their low end we introduce the TinyTPM module, which enforces trustworthy operation and IP protection for embedded
systems. Our approach covers the following two key principles: trustworthy attestation of the embedded system state and IP protection by providing authenticated and encrypted update procedures for FPGAs. The TinyTPM consumes only a few resources and is therefore well-suited to design secure, efficient, and low cost FPGA-based embedded systems.
The high end of IT systems is addressed by the Dynamic-Context TPM architecture, which is aimed to satisfy the needs of each participant to multiple stakeholder applications. In such scenarios, a TPM has to attest the state of their applications on the platform to each stakeholder and to additionally protect their individual assets. The architecture detailed in this presentation supports not only off-the-shelf software-based TPMs, but also dedicated hardware TPMs (or a combination of both) for each stakeholder. As an additional asset, this approach enables a dynamic exchange of contexts (TPM instances) without any modication of the underlying architecture.
The presented novel TPM architectures have been implemented as a proof-of-concept on top of a Xilinx Virtex-5 FPGA platform using softcore processors and dedicated hardware modules. Their specific advantages in terms of security and efficiency are demonstrated for several test cases.
Sorin Alexander Huss received the Dipl.-Ing. and Dr.-Ing. degrees in
electrical engineering from Technische Universitaet Munchen, Munich, Germany,
in 1976 and 1982, respectively. He worked in industry from 1982 until 1990 in
different positions with AEG Aktiengesellschaft in Ulm, Germany. From 1986 to
1990 he headed the CAD/CAE department of the AEG Integrated Circuits Design
Center. During his time in industry he initiated and managed several major
national and European research projects.
Since 1990, he has been a full professor in the Computer Science Department of
Technische Universitaet Darmstadt, Germany, and also a faculty member of the
Electrical Engineering and Information Technology Department of the same
university. Dr. Huss was from 2009 until June 2011 one of the founders and
directors of the "CASED Center for Advanced Security Research Darmstadt"
heading the "Secure Things" research group. He authored or coauthored two
books, many book chapters, and more than 240 reviewed journal and conference
papers. He received several international Best Paper, Outstanding Achievement,
and Academic Awards.
His current research interests are in the areas of embedded systems design
methodology, reconfigurable HW/SW architectures for IT security applications,
and future car-to-car communication systems. Professor Huss is a member of
ACM, IEEE, German Computer Science Association (GI), and German Information
Technology Society (ITG). He was general chair of several international
conferences and serves as a member of many conference program committees and
editorial boards. Dr. Huss works in addition to his academic duties as a
scientific consultant to the European Union, to the German Research Foundation,
and to major German as well as to international companies.
Prof. Cetin Kaya Koc
Professor, IEEE Fellow
Department of Computer Science
University of California Santa Barbara
Topic: Security Analysis of 3-D Integrated Crypto Co-processors
3-D integration presents many new opportunities for architects and embedded
systems designers. However, 3-D integration has not yet been explored by the
cryptographic hardware community. Traditionally, crypto coprocessors have been
implemented as a separate die or by utilizing one or more cores in a chip
multiprocessor. These methods have their drawbacks and limitations in terms of
tamper-resistance, side-channel immunity and performance. In this work we
propose a new class of co-processors that are "snapped-on" to the main
processor using 3-D integration, and we investigate their security
ramifications. These 3-D co-processors hold many advantages over previous
implementations. This paper begins with an overview of 3-D integration and its
prior applications.We then outline security threat models relevant to crypto
co-processors and discuss the advantages and disadvantages of using a dedicated
3-D crypto co-processor compared to traditional, commodity, off-chip crypto
co-processors. We also discuss the performance improvements that can be gained
from using a 3-D approach.
This work was jointly performed by J. Valamehr (UCSB), T. Huffmire (NPS), C.
Irvine (NPS), R. Kastner (UCSD), C. K. Koc (UCSB & SEHIR), T. Levin (NPS), T.
Cetin Kaya Koc received his Ph.D. in Electrical & Computer
Engineering from University of California Santa Barbara in 1988. He was an
Assistant Professor at University of Houston (1988-1992), Assistant, Associate
and Full Professor at Oregon State University (1992-2007). He established
Information Security Laboratory at Oregon State University, and received Award
for Outstanding and Sustained Research Leadership in September 2001. His
research interests are in cryptographic hardware and embedded systems, secure
hardware design, side-channel attacks and countermeasures, algorithms and
architectures for computer arithmetic and finite fields. Koc is the co-founder
of the Workshop on Cryptographic Hardware and Embedded Systems (CHES:
chesworkshop.org) with Christof Paar, which started in 1999. The CHES Workshop
is the second largest cryptography conference after Crypto and the premier
forum for presenting scientific advances in all aspects of cryptographic
hardware and security of embedded systems.
Recently, Koc has also collaborated with a group of European mathematicians and
engineers and co-founded a new conference, International Workshop on the
Arithmetic of Finite Fields (WAIFI: waifi.org). It is a forum of engineers and
mathematicians interested in efficient software and hardware realizations of
finite fields. The first and second WAIFIs were held in Madrid (2007) and Siena
(2008); The third WAIFI was in Istanbul in June 2010. In addition to serving as
a member of the steering committee, Koc was the program co-chair of WAIFI 2008
and the general co-chair of WAIFI 2010. Koc has also been in the editorial
boards of IEEE Transactions on Computers (2003-2008) and IEEE Transactions on
Mobile Computing (2003-2007). Furthermore, he was a guest co-editor of two
issues (April 2003 & November 2008) of IEEE Transactions on Computers on
cryptographic and cryptanalytic hardware and embedded systems.
Koc was elected as IEEE Fellow in 2007 for his contributions to cryptographic
Koc is the founding Editor-in-Chief of Journal of Cryptographic Engineering, a
new Springer journal, covering research areas of the CHES Workshop; the first
issue will be published in March 2011. Koc is the co-author of the book
Cryptographic Algorithms on Reconfigurable Hardware, published by Springer in
2007, and the editor and co-author of the book Cryptographic Engineering, also
published by Springer in 2009. In addition to contributing to 6 conference
proceedings as co-editor, he has also authored or co-authored more than 120
journal and conference papers, and 8 US patents and 3 applications.
Prof. Wayne Luk
Professor of Computer Engineering, IEEE Fellow, BCS Fellow
Imperial College London
Topic: Efficiency and productivity challenges in reconfigurable computing
In the last few decades, reconfigurable computing systems are becoming
increasingly widespread, particularly for demanding applications ranging from
financial modelling to medical imaging. However, as design complexity grows,
reconfigurable computing can only remain competitive if key challenges, such as
enhancing design efficiency while improving designer productivity, are met.
This talk examines recent advances in design methods and tools that address
such challenges in reconfigurable computing, and suggests some promising
research directions for the future.
Wayne Luk is Professor of Computer Engineering with Imperial
College London. He was a Visiting Professor with Stanford University,
California, and with Queen's University Belfast, UK. His research includes
theory and practice of customizing hardware and software for specific
application domains, such as multimedia, financial modeling, and medical
computing. His current work involves high-level compilation techniques and
tools for high-performance computers and embedded systems, particularly those
containing accelerators such as FPGAs and GPUs. He received a Research
Excellence Award from Imperial College London, and 11 awards for his
publications from various international conferences. He is a Fellow of the IEEE
and the BCS.
Mr. Grant Martin
Topic: "ARC for Better Living": The future of (re-)configurable technology
Interest in runtime reconfigurable computing technology has grown, especially
by the academic community, but the practical applications of it remain limited.
However, configurable computing technology has been growing in importance in
many real products and will continue to do so in the next several years. There
are many reasons for this, including efficiency and increased computational
throughput. However, if we can sum up the interest in configurable
computational in one word, that word is "Energy". This has a special impact
on battery-powered, handheld devices, but also has significant ramifications
for larger devices where configurable computing technology can play. And
configurable, extensible processors are the best version of configurable
computing technology around. Multicore configurable computation further
minimises energy consumption. If energy conservation and efficiency is key to
Better Living, configurable computation is one of the best ways to achieve it.
Grant Martin is a Chief Scientist at Tensilica, Inc. in Santa Clara,
California. Before that, Grant worked for Burroughs in Scotland for 6 years;
Nortel/BNR in Canada for 10 years; and Cadence Design Systems for 9 years,
eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's
and Master's degrees in Mathematics (Combinatorics and Optimisation) from the
University of Waterloo, Canada, in 1977 and 1978.
Grant is a co-author or co-editor of ten books dealing with SoC design,
SystemC, UML, modelling, EDA for integrated circuits and system-level design,
including the first book on SoC design published in Russian. His most recent
book, "ESL Models and their Application: Electronic System Level Design and
Verification in Practice", written with Brian Bailey, was published by Springer
in January, 2010. He is a co-editor of the Springer Embedded Systems Series.
He was co-chair of the DAC Technical Programme Committee for Methods for 2005
and 2006. His particular areas of interest include IP-based design of
system-on-chip, platform-based design, and baseband processing. Grant is a
Senior Member of the IEEE.
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