Publications
Publications
Latest list please refer to the research group page http://www4.ee.cityu.edu.hk/CALAS/
Journal papers
•M.K. Jaiswal, R.C.C. Cheung, M. Balakrishnan, K. Paul, "Series Expansion based Efficient Architectures for Double Precision Floating Point Division", Circuits, Systems & Signal Processing, May, 2014. |
•M.K. Jaiswal, R.C.C. Cheung, M. Balakrishnan, K. Paul, "Unified Architecture for Double / Two-Parallel Single Precision Floating Point Adder", IEEE Transactions on Circuits and Systems II, to appear, 2014. |
•Y. Xin, W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, Y. Hong, S. Dong, T.W. Berger, "An FPGA based Scalable Architecture of a Stochastic State Point Process Filter (SSPPF) to Track the Nonlinear Dynamics Underlying Neural Spiking", Microelectronics Journal, to appear, 2014. |
•Z. Ullah, M.K. Jaiswal, R.C.C. Cheung, "E-TCAM: An Efficient SRAM-based Architecture for TCAM", Circuits, Systems & Signal Processing, to appear, 2014. |
•C. Wang, X. Li, J. Zhang, P. Chen, Y. Chen , X. Zhou, R.C.C. Cheung, "Architecture Support for Task Out-of-order Execution in MPSoCs", IEEE Transactions on Computers, to appear, 2014. |
•Z. Ullah, M.K. Jaiswal, R.C.C. Cheung, "Z-TCAM: An SRAM-based Architecture for TCAM", IEEE Transactions on VLSI Systems, to appear, 2014. |
•H. Gu, D. Gu, W. Xie, R.C.C. Cheung, "Efficient Pairing Computation on Huff Curves", Cryptologia, to appear, 2014. | PDF
•H. Luo, Y. Han, R.C.C. Cheung, T. Cao, X. Liu, F. Gao, "A Sigma-Delta Modulator using Gain-boost Class-C Inverter For Audio Applications", Journal of Circuits, Systems and Computers, Vol. 22, No. 10, pp. 1340024, 2013. | PDF
•H. Zhou, K.M. Shum, R.C.C. Cheung, and C.H. Chan, "High-data-rate FSK demodulator for wireless communication", Electronics Letters, Vol. 49, No. 21, pp. 1353-1355, Oct, 2013. | PDF
•J. Hu, J. Wei, W. Guo, and R.C.C. Cheung, "Montgomery Multiplier over F2m", IEICE Electronics Express (ELEX), 2013, to appear. | PDF
•H. Luo, Y. Han, R.C.C. Cheung, X. Liu, and T. Cao, "A 0.8-V 230-uW 98-dB DR Inverter-Based Sigma-Delta Modulator for Audio Applications", IEEE Journal of Solid-State Circuits, Vol 48(10), pp. 2430-2441, Oct, 2013. | PDF
•B.B. Liu, Y.W. Yu, D.Z. Wang, R.C.C. Cheung, H. Yan, "Design Exploration of Geometric Biclustering for Microarray Data Analysis in Data Mining", IEEE Transactions on Parallel and Distributed Systems, IEEE, to appear, 2013.
•B.B. Liu, Y. Xin, R.C.C. Cheung, H. Yan, "GPU-based Biclustering for Microarray Data Analysis in Neurocomputing", Neurocomputing Journal, Elsevier, to appear, 2013.
•X. Yao, B.B. Liu, B. Min; W.X.Y. Li, R.C.C. Cheung, A.S. Fong, T.F. Chan, "Parallel Architecture for DNA Sequence Inexact Match with Burrows-Wheeler Transform", Microelectronics Journal, Elsevier, to appear, 2013.
•G. Yao, J.F. Fan, R.C.C. Cheung, I. Verbauwhede "Novel RNS Parameter Selection for Fast Modular Multiplication", IEEE Transactions on Computers, to appear, 2013. | PDF
•W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, D. Song, T.W. Berger, "Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA", IEEE Transactions on Biomedical Circuits and Systems, Vol. 7, Issue 4, pp. 489-498, Aug, 2013 | PDF.
•D. Pao, N.L. Or, R.C.C. Cheung, "A Memory-Based NFA Regular Expression Match Engine for Signature-Based Intrusion Detection Computer Communications", Computer Communications, Elsevier, In Press, 2013. | PDF
•M. Jaiswal, and R.C.C. Cheung, "Area-Efficient Architectures for Double Precision Multiplier on FPGA, with Run-time-Reconfigurable Dual Single Precision Support", Microelectronics Journal, Springer, Vol. 44, Issue 5, pp 421-430, 2013. | PDF
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Y. Han, X.P. Liu, X.X. Han, H. Luo, Ray C.C. Cheung, T.L. Cao, "A low-power inverter-based Sigma-Delta ADC for audio applications", SCIENCE CHINA Information Sciences, to appear, 2013,
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B. Min, R.C.C. Cheung, and H. Yan, "A Flexible and Customizable Architecture for Relaxation Labeling Algorithm", in IEEE Transactions on Circuits and Systems II (TCAS-2), Vol. 60, Issue 2, pp. 106-110, 2013.| PDF
•H. Luo, Y. Han, R.C.C. Cheung, G. Liang, D. Zhu, "Subthreshold CMOS voltage reference circuit with body bias compensation for process variation", IET Circuits, Devices & Systems, Vol. 6(3), 198-203, 2012. PDF.
•M. Jaiswal, and R.C.C. Cheung, "VLSI Implementation of Double Precision Floating-Point Multiplier using Karatsuba Technique", Circuits, Systems & Signal Processing (CSSP), Springer, Feb 2013, Vol. 32, Issue 1, pp 15-27. | PDF
•H. Fan, Y.L. Wu, and R.C.C. Cheung, "Design Automation Framework for Reconfigurable Interconnection Networks", The Computer Journal 2012; doi: 10.1093/comjnl/bxs136. |
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•J. Sum, C. Leung, R.C.C. Cheung, and T. Ho, "HEALPIX DCT technique for compressing PCA-based illumination adjustable images", Neural computing & Applications, 21, 2012 | PDF.
• Z. Wang, C.W. Yu, R.C.C. Cheung, H. Yan, "Hypergraph based Geometric Biclustering Algorithm", Pattern Recognition Letters, Available online 22 May 2012, ISSN 0167-8655, 10.1016/j.patrec.2012.05.001. |
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• Will X.Y. Li, Rosa H.M. Chan, Wei Zhang, R.C.C. Cheung, Dong Song, Theodore W. Berger, "High-performance and Scalable System Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), pp. 489-501, 2011. | PDF
•M. Jaiswal, and R.C.C. Cheung, "High Performance FPGA Implementation of Double Precision Floating Point Adder/Subtractor", International Journal of Hybrid Information Technology, SERSC, Oct, 2011 | PDF
•Z. Hao, H. Xiaowei, H. Yan, R.C.C. Cheung, H. Xiaoxia, W. Hao, and L. Guo, "An 18-bit high performance audio sigma-delta D/A converter", in Journal of Semiconductors, 31(7), 2010 | PDF
•Hao Luo, Yan Han, R.C.C. Cheung, Xiaoxia Han, and Dazhong Zhu, "Bulk-compensated technique and its application to sub-threshold ICs", in Electronic Letters, 46(16), pp. 1105-1106, 2010. | PDF
•Luo Hao, Han Yan, Ray C. C. Cheung, Han Xiaoxia, Ma Shaoyu, Ying Peng and Zhu Dazhong, "A high-performance, low-power Sigma-Delta ADC for digital audio applications", in Journal of Semiconductors, Volume 31, Issue 5, 2010. | PDF
•D. Lee, R.C.C. Cheung, W. Luk, and J.D. Villasenor, "Hierarchical Segmentation for Hardware Function Evaluation", in IEEE Transactions on VLSI Systems, 17(1), Jan, 2009. | PDF
•D. Lee, R.C.C. Cheung, W. Luk, and J.D. Villasenor, "Hardware Implementation tradeoffs of Polynomial approximations and Interpolations", in IEEE Transactions on Computers, Vol.57(5), pp.686-701, May,2008. | PDF
•R.C.C. Cheung, D. Lee, W. Luk, and J.D. Villasenor, "Hardware Generation of Arbitrary Random Number Distributions from Uniform Distributions via the Inversion Method", in IEEE Transactions on Very Large Scale Integration Systems, Vol. 15(8), 952-962, August, 2007. | PDF
•D. Lee, R.C.C. Cheung, and J.D. Villasenor, "A Flexible Architecture for Precise Gamma Correction ", in IEEE Transactions on Very Large Scale Integration Systems, Vol. 15(4), 474-478, April, 2007. | PDF
•H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "The Exact Channel Density Bound and Compound Design for Generic Universal Switch Blocks," in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 12(2), April, 2007. | PDF
•D. Lee, A. Abdul Gaffar, R.C.C. Cheung, O. Mencer, W. Luk, and G.A. Constantinides, "Accuracy Guaranteed Bit-Width Optimization", in IEEE Transactions on Computer-Aided Design, Vol. 25(10), 1990-2000, October, 2006. | PDF
•H. Fan, Y.L. Wu, C.C. Cheung and J. Liu, "Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes," in IEEE Transactions on Computers, Vol. 55(4), pp. 373-384, April, 2006. | PDF
•R.C.C. Cheung, N. Telle, W. Luk, and P.Y.K. Cheung, "Customisable Elliptic Curve Cryptosystems", in IEEE Transactions on Very Large Scale Integration Systems, Vol. 13(9), pp. 1048-1059, September, 2005. | PDF
•H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "On Optimal Hyper-universal and Rearrangeable Switch Box Designs," in IEEE Transactions on Computer-Aided Design, Vol. 22(12), pp. 1637-1649, December, 2003. | PDF
•Y.L. Wu, C.C. Cheung, D.I. Cheng, and H.B. Fan, "Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques," in IEEE Transactions on Very Large Scale Integration Systems, Vol. 11(3), pp. 451-460, June, 2003. | PDF
Conference papers
Biomedical and Bioinformatic Circuit Designs
•W.X.Y. Li, Y. Xin, S. Dong, T. Berger and R.C.C. Cheung, "VLSI Architecture of a High-Performance Neural Spiking Activity Simulator based on High-Order Volterra Kernels", International Symposium on Integrated Circuits (ISIC) 2014, to appear.
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N.Y. Song, J. Nicod, B. Min, R.C.C Cheung, M.A. Amin, H. Yan, "Noise filtering and occurrence identification of mouse ultrasonic vocalization call", to appear, IEEE International Conference on Machine Learning and Cybernetics, Tianjin, 2013.|
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Y. Xin, W.X.Y. Li, B. Min, Y. Han, R.C.C. Cheung, "A Customizable Stochastic State Point Process Filter (SSPPF) for Neural Spiking Activity", to appear, EMBC'13, Osaka, 2013.|
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W.X.Y. Li, R.C.C. Cheung, R.H.M. Chan, D. Song, and T.W. Berger, "A Reconfigurable Architecture for Real-Time Prediction of Neural Activity", to appear, ISCAS'13, Beijing, 2013.| PDF
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C. Wang, X. Li, X. Zhou, J. Martin and R.C.C. Cheung, "Genome Sequencing Using MapReduce on FPGA with Multiple Hardware Accelerators", to appear, FPGA, 2013.
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A.W.Y. Lo, B. Liu, and R.C.C. Cheung, "GPU-Based Biclustering for Neural Information Processing", the 19th International Conference on Neural Information Processing (ICONIP2012), Qatar, Nov, 2012.
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W. Li, R.H.M. Chan, W. Zhang, R.C.C. Cheung, D. Song, and T.W. Berger, " FPGA-Based Prototyping of Generalized Laguerre-Volterra MIMO Model for Neural Science Research", International conference on Field-Programmable Logic and Applications (FPL), Greece, Sept, 2011.
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W. Li, R.C.C. Cheung, W. Zhang, R.H.M. Chan, D. Song, and T.W. Berger, "FPGA architecture of generalized laguerre-volterra MIMO model for neural population spiking activities", International symposium on Field-Programmable Custom Computing Machines, FCCM, 2011.
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P. Zhu, R.C.C. Cheung, H. Li, L. Cui, and B. Hu, "FPGA-based Acceleration for Graph Similarity", Design, Automation and Test in Europe, March, 2011.
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C.W. Yu, Z. Wang, R.C.C. Cheung, and H. Yan, "An FPGA-based Geometric Biclustering Accelerator for Genes microarray Data Analysis", Design, Automation and Test in Europe, March, 2011.
Cryptographic hardware designs
•M. Stottinger, G.X.X. Yao, and R.C.C. Cheung, "Zero Collision Attack and its Countermeasures on Residue Number System Multipliers", International Symposium on Integrated Circuits (ISIC) 2014, to appear.
•H. Gu, W. Xie, and R.C.C. Cheung, "Analysis The Montgomery Ladder Algorithm For Elliptic Curves over Ternary Fields", 2013 International Conference on Information and Network Security (ICINS 2013), to appear.
•J. Zhang, Y. Lin, Y. Lu, R.C.C. Cheung, W. Che and J. Bian, "Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits", FCCM, 2013.
•D. Chen, G.X. Yao, C.K. Koc, R.C.C. Cheung, "Low complexity and hardware-friendly spectral modular multiplication", pp. 368-375, FPT, South Korea, 2012. | PDF
•B. Min, R.C.C. Cheung, and Y. Han, "FPGA-based High-Throughput and Area-Efficient Architectures of the Hummingbird Cryptography", the 37th Annual Conference of the IEEE Industrial Electronics Society (IECON), Melbourne, Australia, Nov, 2011.
•R.C.C. Cheung, S. Duquesne, J. Fan, N. Guillermin, I. Verbauwhede, G.X. Yao, "FPGA Implementations of Pairing using Residue Number System and Lazy Reduction", International Workshop on Cryptographic Hardware and Embedded Systems(CHES), Nara, Japan, Oct, 2011.
•J. Szefer, W. Zhang, Y.Y. Chen, D. Champagne, K. Chan, X.Y. Li, R.C.C. Cheung, and R. Lee, "Rapid Single-Chip Secure Processor Prototyping on OpenSPARC FPGA Platform", IEEE International Symposium on Rapid System Prototyping (RSP), Germany, 24-27 May 2011.
•X. Yao, R.C.C. Cheung, C.K. Koc, and K.F. Man, "Reconfigurable number theoretic transform architectures for cryptographic applications", 2010 International Conference on Field-Programmable Technology, FPT'10, Beijing, PRC, 8-10 December 2010, pp 308-311.
•X. Yao, R.C.C. Cheung, and K.F. Man, "Counter Embedded Memory Architecture for Trusted Computing Platform", to appear in Proceedings of the IEEE Symposium on Rapid System Prototyping (RSP), Virginia, USA, 2010.
•R.C.C. Cheung, C.K. Koc, and J.D. Villasenor, "A High-Performance Hardware Architecture for Spectral Hash Algorithm", to appear in Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Boston, MA, USA, 2009.
•R.C.C. Cheung, W. Luk, and P.Y.K. Cheung, "Reconfigurable Elliptic Curve Cryptosystem on a Chip", in Proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 24-29, Vol. 1, March, Munich, Germany, 2005. | PDF
•R.C.C. Cheung, A. Brown, W. Luk, and P.Y.K. Cheung, "A Scalable Hardware Architecture for Prime Number Validation", in Proceedings of IEEE International Conference on Field Programmable Technology (FPT), pp. 177-184, Dec, Brisbane, Australia, 2004. | PDF
•N. Telle, W. Luk and R.C.C. Cheung, "Customising Hardware Designs for Elliptic Curve Cryptography", in Proceedings of the International Workshop on Systems, Architectures, Modeling and Simulation (SAMOS'04), pp. 274-283, Samos, Greece, 2004.
Computer Arithmetic
•M.K. Jaiswal, R.C.C. Cheung, M. Balakrishnan, K. Paul, "Configurable Architecture for Double / Two-Parallel Single Precision Floating Point Division", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), to appear, 2014. |
•M.K. Jaiswal, and R.C.C. Cheung, "Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier", to appear in IEEE International Conference on Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, May, 2012. |
•M.K. Jaiswal, and R.C.C. Cheung, "Area-Efficient Architectures for Large Integer and
Quadruple Precision Floating Point Multipliers", in IEEE International Conference on Field-Programmable Custom Computing Machines (FCCM 2012), Toronto, Canada, April, 2012. | PDF
•Z. Ullah, M.K. Jaiswal, Y.C. Chan, and R.C.C. Cheung, "FPGA Implementation of SRAM-basedTernary Content Addressable Memory", to appear in IEEE International Conference on Reconfigurable Architectures Workshop (RAW 2012), Shanghai, China, May, 2012. |
•M.K. Jaiswal, and R.C.C. Cheung, "High Performance Reconfigurable Architecture for Double Precision Floating Point Division", to appear in International Symposium on
Applied Reconfigurable Computing (ARC 2012), Hong Kong, China, March, 2012. |
•W. Osborne, J. Coutinho, R.C.C. Cheung, W. Luk, and O. Mencer, "Instrumented Multi-stage Word-length Optimization", to appear in IEEE International Conference on Field-Programmable Technology, Japan, Dec, 2007. | PDF
•W. Osborne, R.C.C. Cheung, J. Coutinho, and W. Luk, "Automatic Accuracy Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems", to appear in IEEE International Conference on Field-Programmable Logic and Applications (FPL), Netherlands, Aug, 2007. | PDF
•D. Lee, R.C.C. Cheung, J.D. Villasenor, and W. Luk, "Inversion-based hardware Gaussian random number generator: a case study of function evaluation via hierarchical segmentation", in IEEE International Conference on Field-Programmable Technology (FPT), pp. 33-40, Bangkok, Thailand, Dec, 2006. | PDF | Slides
•R.C.C. Cheung, D. Lee, O. Mencer, W. Luk, and P.Y.K. Cheung, "Automating Custom-Precision Function Evaluation for Embedded Processors", in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 22-31, San Francisco, Sept, 2005. | PDF | Slides
•G.L. Zhang, P.H.W. Leong, D. Lee, J.D. Villasenor, R.C.C. Cheung and W. Luk, Hardware architecture for a Ziggurat-based Gaussian random number generator, in IEEE International Conference on Field Programmable Logic and its Applications (FPL), pp. 275-280, Finland, Aug, 2005. |PDF
•G.L. Zhang, P.H.W. Leong, C.H. Ho, K.H. Tsoi, C.C.C. Cheung, D. Lee, R.C.C. Cheung and W. Luk, "Reconfigurable Acceleration for Monte Carlo based Financial Simulation", in IEEE International Conference on Field-Programmable Technology (FPT), pp. 215-222, Singapore, Dec, 2005. | PDF | Slides
Digital Circuit Designs
•P. Zhu, C. Zhang, H. Li, R.C.C. Cheung, B. Hu, "An FPGA-Based Acceleration Platform for Auction Algorithm ", in Proceedings of the IEEE International Symposium on Circuits & Systems ISCAS'12, Seoul, Korea, May, 2012. | PDF
•R.C.C. Cheung, K.P. Pun, Steve C.L. Yuen, K.H. Tsoi and Philip H.W. Leong, "An FPGA-based Re-configurable 24-bit 96kHz Sigma-Delta Audio DAC", in Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 110-117, Tokyo, Japan, Dec, 2003. |PDF
•P.K. Tsang, C.C. Cheung, K.H. Leung, T.K. Lee and and P.H.W. Leong, "An Asynchronous Forth Microprocessor", Proceedings of the IEEE Region 10 Conference (TENCON), Vol. 2, pp. 1079-1082, Korea, 1999.
Mobile communication designs
•S. Joshi, R.C.C. Cheung, P. Monajemi, and J.D. Villasenor, "Traffic-based Study of Femtocell Access Policy Impacts on HSPA Service Quality", to appear in Proceedings of IEEE International Globecom 2009 Communications Quality of Service, Reliability and Performance Modeling Symposium (GC'09 CQRPM), Hawaii, USA, 2009.
Computer Aided Designs (CAD)
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C.W. Yu, F. Cox, W. Luk, and R.C.C. Cheung, "Hydrate: Hybrid Reconfigurable Architecture Expressions", International conference on Field-Programmable Technology (FPT), India, Dec, 2011.
•H. Fan, Y.L. Wu, and C.C. Cheung, "Design Automation for Reconfigurable Interconnection Networks", in Proceedings of the Applied Reconfigurable Computing (ARC), Bangkok, Thailand, 2009.
•L. Zhou, C.C. Cheung and Y.L. Wu, "What if Merging Connection and Switch Boxes --- an Experimental Revisit on FPGA Architectures", in Proceedings of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1295-1299, Vol. 2, June, Chengdu, China, 2004. (received Best Paper Award) | PDF
•H. Fan, Y.L. Wu, C.C. Cheung and J. Liu, "On Optimal Irregular Switch Box Designs", in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL), LNCS 3203, pp. 189-199, Antwerp, Belgium, 2004. | PDF | Slides
•H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "On Optimum Designs of Universal Switch Blocks," in Proceedings of International Conference on Field Programmable Logic and Applications (FPL), LNCS 2438, pp. 142-151, Montpellier, France, 2002. | PDF | Slides
•H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "On Optimum Switch Box Designs for 2-D FPGAs, in Proceedings of IEEE/ACM Design Automation Conference (DAC), pp. 203-208, Las Vegas, June, 2001. | Slides
•Y.L. Wu, H. Fan, W. Wong, K.C. Cheng, and C.C. Cheung, "On Strong Locality Properties of Alternative Wires in Digital Circuits," in Proceedings of Workshop on Synthesis And System Integration of MIxed technologies (SASIMI), pp. 244-250, Hiroshima, Japan, 2003. | Slides
•Y. L. Wu, C.N. Sze, C.C. Cheung and H. Fan, "On Improved Graph-Based Alternative Wiring Scheme for Multi-Level Logic Optimization", IEEE International Conference in Electronics Circuits and Systems (ICECS), Lebanon, 2000.
•C.C. Cheung, Y.L. Wu, and D.I. Cheng, "Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques," in Proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 233-239, March, Munich, Germany, Mar, 2001. | Slides
Poster Papers
•R.C.C. Cheung and A. Brown, "A Scalable System-on-a-chip Architecture for Prime Number Validation", in the IEE SoC Design, Test and Technology Postgraduate Seminar, Loughborough, United Kingdom, 2004. | PDF
•R.C.C. Cheung, "A System on Chip Design Framework for Prime Number Validation using Reconfigurable Hardware", in the International Conference on Field Programmable Logic and Applications (FPL) (PhD Forum), LNCS 3203, pp. 1186-1187, Antwerp, Belgium, 2004.
Miscellaneous
•R.C.C. Cheung, "Customisable Arithmetic Hardware Designs", Ph.D. thesis, Department of Computing, Imperial College, University of London, May, 2007.
•R.C.C. Cheung, "Design methods for Cryptographic Field-Programmable System-on-Chip (cFPSoC)", MPhil/PhD transfer report, Department of Computing, Imperial College, University of London, June, 2005.
•R.C.C. Cheung, "Customisable Cryptographic Hardware Designs", 9-month progress report, Department of Computing, Imperial College, University of London, Nov, 2004.
•C.C. Cheung, "Multi-way Partitioning with Logic Perturbation technique and Hyper-Universal Switch-Box Routing for Field-Programmable Gate Arrays", Master's thesis, The Chinese University of Hong Kong, 2001. | Slides
•C.C. Cheung, "CMOS Implementation of a Forth Microprocessor", Final Year Project Report, The Chinese University of Hong Kong, 1999.
•C.C. Cheung, "SIS Logic Synthesis Tutorial", CAD group meeting, The Chinese University of Hong Kong, 2003. | Slides
•C.C. Cheung, "Global Flow Optimization in TCAD'91", CAD group meeting, The Chinese University of Hong Kong, 2003. | Slides