IEEE ICFPT 2002

Preliminary Technical Programme

Monday 16 December 2002

0800-1830

Registration

0830-0845

Welcome

0845-0900

Special Keynote: Paul Y.S. Cheung, Policy Advisor,

Innovation and Technology Commission, Hong Kong Government

Title: Technology Research and Development in Hong Kong: Hype or Reality

0900-0940

Keynote: Tsugio Makimoto, Sony Corporation

Title: The Hot Decade of Field Programmable Technologies

Session 1: Networking Applications

0940-1005

Code : 12

Paper : Real-time Packet Editing Using Reconfigurable Hardware for Active

Networking

Authors : T. Miyazaki, T. Murooka, N. Takahashi, M. Hashimoto

1005-1030

Code : 69

Paper : Implementation of an FPGA Based Accelerator for Virtual Private

Networks

Authors : O. Y. H. Cheung and P. H. W. Leong

1030-1110

Coffee and Poster Session 1

Session 2: Run-time Reconfiguration Technology

1110-1135

Code : 52

Paper : Compiling Run-Time Parametrisable Designs

Authors : A. Derbyshire and W. Luk

1135-1200

Code : 59

Paper : Adaptive FIR Filter Architectures for Run-Time Reconfigurable

FPGAs

Authors : T. Rissa, R. Uusikartano and J. Niittylahti

1200-1225

Code : 17

Paper : A Methodology for Design of Run-time Reconfigurable Systems

Authors : G. Lee and G. Milne

1225-1250

Code : 75

Paper : Resource-Aware Run-time Elaboration of Behavioural FPGA

Specifiations

Authors : U. Malik, K. So, O. Diessel

1250-1415

Lunch

1415-1455

Keynote: Patrick Lysaght, Xilinx, Inc.

Title: FPGAs as Meta-platforms for Embedded Systems

Session 3: Signal and Matrix Processing

1455-1520

Code : 67

Paper : High-Speed Programmable Sum-of-Power-of-Two (SOPOT)

Finite-Duration Impulses Response (FIR) Filters

Authors : K. S. Yeung and S. C. Chan

1520-1545

Code : 10

Paper : FPGA-based System-level design framework based on the IRIS

synthesis tool and System Generator

Authors : Y. Yi and R. Woods

1545-1610

Code : 65

Paper : Area and Time Efficient Implementation of Matrix Multiplication

on FPGAs

Authors : J. Jang, S. Choi and V. K. Prasanna

1610-1650

Tea and Poster Session 2

Session 4: FPGA-based Applications

1650-1715

Code : 70

Paper : A System Level Implementation of Rijndael on a Memory-slot based

FPGA Card

Authors : D. K. Y. Tong, P. S. Lo, K. H. Lee and P. H. W. Leong

1715-1740

Code : 25

Paper : FPGA-Based Cloud Detection for Real-Time Onboard Remote Sensing

Authors : J. A. Williams, A. S. Dawood and S. J. Visser

1740-1805

Code : 39

Paper : An FPGA-Based Processor for Shogi Mating Problems

Authors : Y. Hori, M. Sonoyama and Tsutomu Maruyama

1805-1830

Code : 76

Paper : Population based Ant Colony Optimization on FPGA

Authors : M. Guntsch, B. Scheuermann, H. Schmeck

Tuesday 17 December 2002

0800-1830

Registration

0900-0940

Keynote: Michael J. Flynn, Stanford University

Title: Programmed Solutions: The step beyond Programmed Logic

Session 5: Reconfigurable and Memory Architectures

0940-1005

Code : 62

Paper : Clustered Programmable-Reconfigurable Processors

Authors : D. B. Gottlieb, J. J. Cook, J. D. Walstrom, S. Ferrera, C. Wang,

N. P. Carter

1005-1030

Code : 72

Paper : Implementing Logic in FPGA Embedded Memory Arrays: Heterogeneous

Memory Architectures

Authors : S. J. E. Wilton

1030-1110

Coffee and Poster Session 3

Session 6: High-Level Design Tools

1110-1135

Code : 41

Paper : Optimising and Adapting High-Level Hardware Designs

Authors : J. G. F. Coutinho and W. Luk

1135-1200

Code : 57

Paper : Floating-Point Bitwidth Analysis via Automatic Differentiation

Authors : A. A. Gaffar, O. Mencer, W. Luk, P. Y. K. Cheung and N. Shirazi

1200-1225

Code : 34

Paper : DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable

Architectures

Authors : Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy

Lauwereins

1225-1250

Code : 38

Paper : A Prolog Based Hardware Description Environment

Authors : K. Benkrid, S. Belkacemi and D. Crookes

1250-1300

Special Presentation: Masahiro Fujita

Title: Presentation on FPT’03 (Tokyo)

1300-1415

Lunch

1415-1455

Keynote: Paul Master, Quicksilver Technology

Title: The Next Big Leap in Reconfigurable Systems

Session 7: Reconfigurable Circuits and Devices

1455-1520

Code : 73

Paper : Gigahertz SiGe BiCMOS FPGAs with new architectures and novel

power management schemes

Authors : K. Zhou, Channakeshav, J. Guo, S. Liu, R. P. Kraft, C. You, J. F.

McDonald

1520-1545

Code : 21

Paper : Evolutionary Analog Circuit Design on a Programmable Analog

Multiplexer Array

Authors : C. C. Santini, J. F. M. Amaral, M. A. C. Pacheco, M. M. Vellasco

1545-1610

Code : 01

Paper : An Optically Differential Reconfigurable Gate Array and its Power

Consumption Estimation

Authors : Minoru Watanabe and Fuminori Kobayashi

1610-1650

Tea and Poster Session 4

Session 8: Technology Mapping and Layout Tools

1650-1715

Code : 14

Paper : A Technology Mapping Algorithm for CPLD Architectures

Authors : S. Chen, T. T. Hwang and C. L. Liu

1715-1740

Code : 16

Paper : Power-Aware Technology Mapping for LUT-Based FPGAs

Authors : J. H. Anderson and F. N. Najm

1740-1805

Code : 09

Paper : Synthesizing Datapath Circuits for FPGAs with Emphasis on Area

Minimization

Authors : A. Ye, J. Rose, D. Lewis

1805-1830

Code : 24

Paper : The Effect of Cluster Packing and Node Duplication Control in

Delay Driven Clustering

Authors : M. E. Dehkordi and S. D. Brown

1930-2330

Conference Dinner (Victoria Harbour Cruise)

Wednesday 18 December 2002

0800-1250

Registration

0900-0940

Keynote: Erik Cleage, Altera Corporation

Title: The Economics of FPGAs, ASSPs & ASICs

Session 9: Debugging Methods

0940-1005

Code : 46

Paper : Debug Methodology for Arithmetic Circuits on FPGAs

Authors : M. Kubo and M. Fujita

1005-1030

Code : 60

Paper : Debug Methods for Hybrid CPU/FPGA Systems

Authors : E. Roesler and B. Nelson

1030-1110

Coffee and Poster Session

Session 10: Instruction Processors and Systems

1110-1135

Code : 48

Paper : Scalable Acceleration of Inductive Logic Programs

Authors : A. Fidjeland, W. Luk and S. Muggleton

1135-1200

Code : 27

Paper : A Fine-Grained Reconfigurable Logic Array Based on Double Gate

Transistors

Authors : P. Beckett

1200-1225

Code : 35

Paper : A Co-simulation Study of Adaptive EPIC Computing

Authors : V. S. Gheorghita, W. Wong, T. Mitra, S. Talla

1225-1250

Code : 47

Paper : System on Programmable Chip for Real-Time Control Implementations

Authors : D. L. S. Pradel, S. R. Jones, R. M. Goodall

1250-1300

Closing Remarks

POSTER SESSION 1

Code : 02

Paper : A Reconfigurable Vision System for Real-time Applications

Authors : C. T. Huitzil, S. E. M. Rueda and M. A. Estrada

Code : 04

Paper : Loseless Data Compression Programmable Hardware for High-speed Data Networks

Authors : J. L. Nunez and S. Jones

Code : 05

Paper : A Multiplier-less FPGA Core for Image Algebra Neighbourhood Operations

Authors : K. Benkrid

Code : 06

Paper : Multi-hop Routing of Multi-terminal Nets for Evaluation of Hybrid Multi-FPGA Boards

Authors : Sushil Chandra Jain, Anshul Kumar, Shashi Kumar

Code : 07

Paper : Serial-Parallel Tradeoff Analysis Of All-Pairs Shortest Path Algorithms In Reconfigurable Computing

Authors : Sui Tung Mak and Kai Pui Lam

Code : 08

Paper : On-board Satellite Image Compression Using Reconfigurable FPGAs

Authors : A. S. Dawood, J. A. Williams and S. J. Visser

Code : 11

Paper : Efficient Single-Chip Implementation of SHA-384 & SHA-512

Authors : M. McLoone and J. V. McCanny

Code : 13

Paper : An Optimal PCM Codec Soft IP Genereator and Its Application

Authors : G. Wu, L. Chen, Y. Jeang and G. Jong

Code : 15

Paper : Efficient 4-input LUTs FPGA Implementation of Combinatorial Multiplier over Canonical Base GF(16)

Authors : V. Tomashau

Code : 18

Paper : FPGA Based Real-time Adaptive Filtering for Space Applications

Authors : S. J. Visser, A. S. Dawood and J. A. Williams

POSTER SESSION 2

Code : 19

Paper : Diagnosis of Open Defects in FPGA Interconnect

Authors : M. B. Tahoori and E. J. McCluskey

Code : 20

Paper : Testing for Resistive Open Defects in FPGA

Authors : M. B. Tahoori and E. J. McCluskey

Code : 23

Paper : A Novel Parallel Three Phase Genetic Approach To Routing For Field Programmmable Gate Arrays

Authors : A. Muthukaruppan, S. Suresh and V. Kamakoti

Code : 26

Paper : Reconfigurable Implementation of Radiosity Distribution Computation

Authors : J. Y. H. Ko and K. W. Ng

Code : 30

Paper : Specification Of Concurrent Reconfigurable Hardware Using Hardware Join Java

Authors : J. Hopf, G. S. Itzstein and D. Kearney

Code : 31

Paper : Fusion For Uninhabited Airborne Vehicles

Authors : M. D. Jasiunas, D. A. Kearney, J. Hopf and G. B. Wigley

Code : 33

Paper : Compiling Policy Descriptions into Reconfigurable Firewall Processors

Authors : T. K. Lee, S. Yusuf, W. Luk, M. Sloman, E. Lupu and N. Dulay

Code : 36

Paper : Design and Implementation of a Novel Architecture for Symmetric FIR filters with Boundary Handling on Xilinx VIRTEX FPGAs

Authors : A. Benkrid, K. Benkrid and D. Crookes

Code : 37

Paper : Enabling Technologies for Reconfigurable System-on-Chip

Authors : N. W. Bergmann

Code : 40

Paper : FPGA Implementation of MFNN for Image Registration

Authors : M. S. Puranik and D. C. Gharpure

POSTER SESSION 3

Code : 42

Paper : An Efficient Architecture for an Improved Watershed Algorithm and its FPGA Implementation

Authors : C. Rambabu, I. Chakrabarti, A. Mahanta

Code : 43

Paper : The Hardware Implementation of a Genetic Algorithm Model with FPGA

Authors : T. Lei, M. Zhu and J. Wang

Code : 44

Paper : Dynamic reconfiguration for the common key encryption using FPGA

Authors : T. Yamaguchi, T. Hashiyama and S. Okuma

Code : 45

Paper : Field Modifiable Architecture with FPGAs and its Design Methodology

Authors : S. Komatsu, Y. Kojima, H. Saito, K. Seto, M. Fujita

Code : 50

Paper : The Feasibility study of designing a FPGA Multiplier-core on Finite Field

Authors : C. H. Hsu, T. K. Truong, M. H. Jing, W. C. Wu and H. C. Wu

Code : 51

Paper : The Diversity Study of AES on FPGA Application

Authors : M. H. Jing, C. H. Hsu, Y. H. Chen, T. K. Truong and Y. T. Chang

Code : 53

Paper : Speedup Analysis of Simulation-Emulation Co-Operation

Authors : S. G. Miremadi, S. B. Sarmadi, G. Asadi

Code : 54

Paper : Performing Speech Recognition on Multiple Parallel Files Using Continuous Hidden Markov Models on an FPGA

Authors : S. J. Melnikoff, S. F. Quigley and M. J. Russell

Code : 55

Paper : Evolution-enabled reconfigurable computing using field programmable analog devices

Authors : A. Stoica, X. Guo, R. S. Zebulum, M. I. Ferguson and D. Keymeulen

Code : 56

Paper : FPGA-based Free-Form Deformation

Authors : J. Jiang, W. Luk and D. Rueckert

Code : 58

Paper : Incremental Programming for Reconfigurable Engines

Authors : D. Lee, T. K. Lee, W. Luk and P. Y. K. Cheung

POSTER SESSION 4

Code : 63

Paper : Delivering Error Detection Capabilities into a Field Programmable Device: The HORUS Processor Case Study

Authors : F. Rodriguez, J. C. Campelo and J. J. Serrano

Code : 64

Paper : Energy Efficiency of FPGAs and Programmable Processors for Matrix Multiplication

Authors : R. Scrofano, S. Choi and V. K. Prasanna

Code : 66

Paper : Reconfigurable Hardware Control Software Using Anonymous Libraries

Authors : C. Hinkelbein, A. Kugel, R. Manner and M. Muller

Code : 74

Paper : Logic Synthesis of Multi-output Functions for PAL-based CPLDs

Authors : Kania Dariusz

Code : 78

Paper : A Method of Implementing Bit-Serial LDI Ladder Filters in FPGAs Using JBits

Authors : A. Carreira, T. W. Fox and L. E. Turner

Code : 80

Paper : PD-XML: Extensible Markup Language for Processor Description

Authors : S.P. Seng, K.V. Palem, R.M. Rabbah, W.F. Wong, W. Luk, P.Y.K. Cheung

Code : 81

Paper : Sensitivity of FPGA Power Evaluation

Authors : K.K.W. Poon and S.J.E. Wilton

Code : 82

Paper : Pattern Recognition in the HADES – Spectrometer: An Application of FPGA Technology in Nuclear and Particle Physics

Authors : I. Frohlich, A. Gabriel, D. Kirschner, J. Lehnert, E. Lins,

M. Petri, T. Perez-Cavalcanti, J. Ritman, D. Schafer, A. Toia,

M. Traxler and W. Kuehn

Code : 83

Paper : FPGA Education and Research Activities in Taiwan

Authors : Y.T. Chang, Y.T. Chou, W.C. Tsai and C.Y. Lee

Code : 84

Paper : Alternatives in FPGA-based SAD Implementations

Authors : S. Wong, B. Stougie and S. Cotofana

Code : 85

Paper : Strassen’s Matrix Multiplication for Customisable Processors

Authors : H. Ip, J. Low, P.Y.K. Cheung, G. Constantinides, W. Luk,

S.P. Seng and P. Metzgen