Poster Session I
FPGA IMPLEMENTATION OF A FUZZY CONTROLLER FOR AUTOMOBILE DC-DC CONVERTERS
Jacobo Alvarez, Alfonso Lago, Andres Nogueiras, Carlos Martinez-Pe ? alver, Jorge Marcos, Jesus Doval and Oscar Lopez
AN ADAPTIVE AND PREDICTIVE ARCHITECTURE FOR PARAMETERISED PIV ALGORITHMS
Nathalie Bochard, Alain Aubert and Virginie Fresse
A NEW REAL TIME PROGRAMMABLE ENCODER FOR LOW DENSITY PARITY CHECK CODE TARGETING A RECONFIGURABLE INSTRUCTION CELL ARCHITECTURE
Zahid Khan and Tughrul Arslan
TIME-SENSITIVE CONTROL-FLOW CHECKING MONITORING FOR MULTITASK SOCS
Fabian Vargas, Leonardo Picolli, Antonio A. de Alecrim Jr., Marlon
Moraes and M ? rcio Gama
ACTIVITY-BASED POWER ESTIMATION AND CHARACTERIZATION OF DSP AND MULTIPLIER BLOCKS IN FPGAS
Nathalie Chan King Choy and Steven J. E. Wilton
IMPLEMENTATION OF A REAL-TIME MULTIPLE INPUT MULTIPLE OUTPUT CHANNEL ESTIMATOR ON THE SMART ANTENNA SOFTWARE RADIO TEST SYSTEM PLATFORM USING THE XILINX VIRTEX 2 PRO FIELD PROGRAMMABLE GATE ARRAY
Peter John Green and Desmond P Taylor
EFFICIENT MANAGEMENT OF CUSTOM INSTRUCTIONS FOR RUN-TIME RECONFIGURABLE INSTRUCTION SET PROCESSORS
Siew-Kei Lam, Bharathi N. Krishnan and Thambipillai Srikanthan
FPGA IMPLEMENTATION FOR AN IRIS BIOMETRIC PROCESSOR
Judith Liu-Jimenez, Raul Sanchez-Reillo, Almudena Lindoso and Oscar Miguel-Hurtado
FPGA IMPLEMENTATION OF TABU SEARCH FOR THE QUADRATIC ASSIGNMENT PROBLEM
Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama
Poster Session II
MINIMIZING PEAK POWER FOR APPLICATION CHAINS ON ARCHITECTURES WITH PARTIAL DYNAMIC RECONFIGURATION
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera and Nikil Dutt
HARDWARE JOIN JAVA: A UNIFIED HARDWARE/SOFTWARE LANGUAGE FOR DYNAMIC PARTIAL RUN TIME RECONFIGURABLE COMPUTING APPLICATIONS
David Kearney and John Hopf
AN FPGA BASED GENERIC PROTOTYPING PLATFORM EMPLOYED IN A CMOS LASER DOPPLER BLOOD FLOW CAMERA
Yiqun Zhu, Barrie Hayes-Gill, Steve Morgan and Nguyen Hoang
AN ADAPTIVE VITERBI DECODER ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR
Shohei Abe, Yohei Hasegawa, Takao Toi, Takashi Inuo and Hideharu Amano
POWERBIT - POWER AWARE ARITHMETIC BIT-WIDTH OPTIMIZATION
Altaf Abdul Gaffar, Jonathan A. Clarke and George A. Constantinides
COMBINING HARDWARE RECONFIGURATION AND ADAPTIVE COMPUTATION FOR A NOVEL SOC DESIGN METHODOLOGY
Marco Santambrogio, Vincenzo Rana, Seda Memik and Donatella Sciuto
HARDWARE CHANNEL MODEL FOR ULTRA WIDEBAND SYSTEMS
Wen-Chih Kan and Gerald E. Sobelman
A LEAKAGE AWARE DESIGN METHODOLOGY FOR POWER-GATED PROGRAMMABLE ARCHITECTURES
Narayan Subramanian, Rajarshee Bharadwaj and Dinesh Bhatia
A 'C' COMPILER FOR IMPLEMENTING FPGA BASED BIT-SERIAL DSP SYSTEMS
Dan Cyca and Laurence E. Turner
Poster Session III
PERFORMANCE EVALUATIONS OF RECONFIGME
Grant Wigley and David Kearney
POWER ESTIMATION OF A LUT-BASED MPGA
Francisco-Javier Veredas and Hans-Joerg Pfleiderer
AN FPGA-BASED FLOATING-POINT PROCESSOR ARRAY SUPPORTING A HIGH-PRECISION DOT PRODUCT
Fritz Mayer-Lindenberg
COMMUNICATIONS INFRASTRUCTURE GENERATION FOR MODULAR FPGA RECONFIGURATION
Shannon Koh and Oliver Diessel
FUZZY MODULAR MULTIPLICATION ARCHITECTURE AND LOW COMPLEXITY IPR-PROTECTION FOR FPGA TECHNOLOGY
Abdulrahman Hanoun, Wael Adi and Bassel Soudan
OPTIMAL SET OF BODY BIAS VOLTAGES FOR AN FPGA WITH FIELD-PROGRAMMABLE VTH COMPONENTS
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa and Hanpei Koike
THE COST OF DATA DEPENDENCE IN MOTION VECTOR ESTIMATION FOR RECONFIGURABLE PLATFORMS
Su-Shin Ang, George Constantinides, Wayne Luk and Peter Cheung
COMPARING FLOATING-POINT AND LOGARITHMIC NUMBER REPRESENTATIONS FOR RECONFIGURABLE ACCELERATION
Haohuan Fu, Oskar Mencer and Wayne Luk
DYNAMICALLY RECONFIGURABLE PROTOCOL TRANSDUCER
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu and Masahiro Fujita
Poster Session IV
OPTIMAL TEMPORAL PARTITIONING BASED ON SLOWDOWN AND RETIMING
Christian Plessl, Marco Platzner and Lothar Thiele
MODELING OF GLITCH EFFECTS IN FPGA BASED ARITHMETIC CIRCUITS
Altaf Abdul Gaffar, Jonathan A. Clarke and George A. Constantinides
DESIGN AND VALIDATION OF EXECUTION SCHEMES FOR DYNAMICALLY
RECONFIGURABLE ARCHITECTURES
Tobias Oppold, Sven Eisenhardt and Wolfgang Rosenstiel
PERIODIC LICENSING OF FPGA BASED INTELLECTUAL PROPERTY
Kenneth Kent and Nathaniel Couture
A PERFORMANCE-DRIVEN BIPARTITIONING ALGORITHM FOR MULTI-FPGA
IMPLEMENTATION WITH TIME-MULTIPLEXED I/OS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura and Yoji Kajitani
A STATISTICAL FRAMEWORK FOR DIMENSIONALITY REDUCTION IMPLEMENTATION IN FPGAS
Christos-Savvas Bouganis, Iosifina Pournara and Peter Y.K. Cheung
HARDALIGN: A PARALLEL PAIRWISE ALIGNMENT HARDWARE APPLICATION
Guilherme Luiz Moritz, Heitor Silverio Lopes and Carlos Raimundo Erig Lima
DECOY CIRCUITS FOR FPGA DESIGN PROTECTION
Bradley Christiansen, Yong Kim, Robert Bennington and Christopher Ristich
HARDWARE ARCHITECTURES FOR MONTE-CARLO BASED FINANCIAL SIMULATION
David Thomas, Jacob, Alexis Bower and Wayne Luk
CUSTOMIZABLE FPGA-BASED ARCHITECTURE FOR VIDEO APPLICATIONS IN REAL TIME
Griselda Salda
SUPER FAST HARDWARE STRING MATCHING
Dan Lo
