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IEEE CAS Society

Mahanakorn University of Technology, THAILAND

National Electronics and Computer Technology Center, Thailand






2006 IEEE International Conference on
Field Programmable Technology
December 13-15, 2006 Bangkok Thailand.


Pre- and Post-Conference Workshop

11-12 Dec 2006: Xilinx Professor Workshop
16 Dec 2006: Altera Workshop

Workshop venue: Mahanakorn University of Technology (MUT) - Map

Transportation: Free service will be available at the conference hotel.
Depart time: 7:30 (Hotel) - Arrival time: 8:45 (MUT)
Depart time: 17:15(MUT) - Arrival time: 18:45 (Hot





Xilinx Pre-conference Workshop:
Digital Design with FPGAs

This course provides Professors with an introduction to designing with Xilinx FPGAs using ISE development software tools.
Level: Introductory
Workshop Duration: 2 Days (11-12 Dec 2006)
Who should attend: Professors who are new to FPGAs or Xilinx technology and wish to develop basic labs in Digital Design.
Prerequisites: Digital Design Experience Basic HDL Knowledge (VHDL or Verilog)
Skills Gained: After completing this training, attendees will be able to:
- Implement an FPGA using default options
- Describe Basic Implementation software options
- Determine if performance and utilization goals were met by reading reports
- Assign pin locations and enter global timing constraints with the Constraints Editor
- Build reliable circuits for an FPGA
- Create State Machines using StateCAD
- Create HDL testbenches using HDL Bencher


Day 1: 9am-5pm (Architectures and ISE Flow)

  • Basic FPGA Architecture
  • Xilinx Tool Flow
  • Lab 1: Xilinx tool flow
  • Architecture Wizard and PACE                                         
  • Lab 2: Architecture Wizard and PACE
  • Reading Reports
  • Global Timing Constraints
  • Lab 3: Global Timing Constraints
  • FPGA Design Techniques

Day 2: 9am-5pm (Design intro and Verification)

  • Synchronous Design Techniques
  • Floorplanner
  • Synthesis Techniques
  • Lab 4: Synthesis Techniques
  • Implementation Options
  • Core Generator System
  • Lab 5: Core Generator System
  • Chipscope-Pro
  • Lab 6: Chipscope-Pro



Altera Post-conference Workshop:
Designing with Nios II & SOPC Builder

Level: Basic ~ Intermediate

Course Length: 1 Day

Course Description:

Designing with Nios® II & SOPC Builder course will teach you how easy it is to design in a soft core embedded processor with an Altera® FPGA. This course is focused on the hands-on development of Nios II hardware and software using the Nios® II Development Kit. You will learn how to integrate a Nios II 32-bit microprocessor and test it in an Altera FPGA. You will learn how to configure and compile designs using the Quartus® II and SOPC Builder software tools as well as how develop and run embedded software for Nios II in the Nios II IDE. You will participate in discussions about the features and capabilities of the development board and after taking this course you should feel confident tackling your next system-on-a-programmable-chip (SOPC) design.

Skills Required:

· Background in digital logic design

· Familiar with the PLD development flow

· Some knowledge of programming in C for embedded systems

Skills Developed:

· Gain familiarity with the Altera Quartus II development software

· Knowledge of Nios II embedded processor and the Nios II Development Kit capabilities

· Ability to configure and compile a Nios II embedded processor design using the SOPC Builder tool and Quartus II software

· Clear understanding of the hardware development flow within the Quartus II software, SOPC Builder tool, and ModelSim-Altera -- including how to incorporate custom instructions into a design.

· Understanding of the software development flow using the new Nios II Integrated Development Environment (IDE)--including creating and building software projects, debugging embedded software, project-specific header and library files, and accessing peripherals from C


Introduction to Altera
Designing with Quartus II Software Tool
Lab Exercise 1: Basic Quartus II Design Flow
Nios II Hardware Development
Lab Exercise 2: Nios II Hardware Flow with SOPC Builder
Nios II Software Development & Debug Environment
Lab Exercise 3: Nios II Software Flow
Avalon Switch Fabric
Lab Exercise 4: Designing Custom Peripherals
Custom Instructions & DMA
Lab Exercise 5: Integrating Custom Peripherals and DMA
Conclusion and Q&A