Achievements

Integrated Circuit Design

Phase Lock Loop

Measured results:
Reference frequency: 13MHz
Loop bandwidth: 50kHz
Lock frequency: 2.588~2.829 GHz
Power consumption: 6 mW
Phase Noise: -85.14 dBc/Hz@10kHz
-95.83 dBc/Hz@100kHz
-121.92 dBc/Hz@1MHz

GaAs RFIC Design (1W)


Measured results:
Supply voltage 5V
Maximum linear power (P1dB) 30dBm
Efficiency 45%
Gain 20dB

CMOS RFIC Design

Measured results:
Supply voltage 5V
Gain 14 dBm
Return loss (S11) -14 dB
Maximum linear power (P1dB) 12 dB