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   Submission deadline
11 November 2011
   Author Notification
10 December 2011
   Camera-Ready and Author Registration
29 December 2011
   Conference date
19-23 March 2012

Previous ARC Workshops


Conference Program

  • Preliminary Technical Program page updated! - Jan 27, 2012

  • We are honored to have the following track chairs:

    1. Applied RC Design Methods and Tools

    Brent Nelson, Brigham Young University, USA
    Andreas Koch, Darmstadt University, Germany

    2. Applied RC Architectures

    Yajun Ha, National University, Singapore
    Suhaib Fahmy, Singapore, Nanyang Technological University, Singapore

    3. Applied RC Applications

    George Constantinides, Imperial College London, UK
    Philip Leong, University of Sydney, Australia

    4. Critical Issues in Applied RC

    Lesley Shannon, Simon Fraser University, Canada
    Neil Bergmann, University of Queensland, Australia

    We would like to congratulate the following authors who have contributed to the ARC2012 program.

    Oral presentations

    Qiwei Jin, David Thomas, Diwei Dong, Wayne Luk, Anson H.T. Tse, Gary C.T. Chow and Stephen Weston. Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations

    Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita and Hideharu Amano. Cost Effective Implementation of Flux Limiter Functions using Partial Reconfiguration

    S. Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi and Koen Bertels. The Q^2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms

    Anson H.T. Tse, Gary C.T. Chow, Qiwei Jin, David Thomas and Wayne Luk. Optimising Performance of Quadrature Methods with Reduced Precision

    Karel Heyse, Brahim Al Farisi, Karel Bruneel and Dirk Stroobandt. Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration

    Tassadaq Hussain, Muhammad Shafiq, Miquel Pericas, Eduard Ayguade and Nacho Navarro. PPMC : A Programmable Pattern based Memory Controller

    Kizheppatt Vipin and Suhaib A Fahmy. Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration

    Xuan You Tan, David Boland and George Constantinides. FPGA Paranoia: Testing numerical properties of FPGA floating point IP-cores

    Grigorios Mingas and Christos-Savvas Bouganis. Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware

    Abid Rafique, Nachiket Kapre and George A. Constantinides. A High Throughput FPGA-based Impelementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem

    Wei Ting Loke and Yajun Ha. A Routing Architecture for FPGAs with Dual-VT Switch Boxes and Logic Clusters

    Qiang Liu and Wayne Luk. Heterogeneous Systems for Energy Efficient Scientific Computing

    Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda and Kenji Kise. ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGAs

    Fakhar Anjam, Quan Kong, Roel Seedorf and Stephan Wong. A Run-time Task Migration Scheme for an Adjustable Issue-slots Multi-core Processor

    Hiroki Nakahara, Tsutomu Sasao and Munehiro Matsuura. A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU

    Manish Kumar Jaiswal and Ray C.C. Cheung. High Performance Reconfigurable Architecture for Double Precision Floating Point Division

    Sen Ma, Miaoqing Huang, Eugene Cartwright and David Andrews. Scalable Memory Hierarchies for Embedded Manycore Systems

    Geoffrey Ndu. Boosting Single Thread Performance in Mobile Processors via Recongurable Acceleration

    Florent De Dinechin and Laurent-Stéphane Didier. Table-based division by small integer constants

    Gang Zhou, Li Li and Harald Michalik. Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs

    Takahiro Watanabe and Minoru Watanabe. Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arrays

    Markus Weinhardt. Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform

    Wang Luzhou, Kentaro Sano and Satoru Yamamoto. Domain-Specific Language and Compiler for Stencil Computation on FPGA-based Systolic Computational-Memory Array

    Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai, Ingoo Heo and Yunheung Paek. Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

    Tim Güneysu, Igor L. Markov and Andre Weimerskirch. Securely Sealing Multi-FPGA Systems

    Poster presentations

    Tannous Frangieh, Richard Stroop, Peter Athanas and Teresa Cervero. A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems

    Yarkin Doroz and Erkay Savas. Constructing Cluster of Simple FPGA boards for Cryptologic Computations

    Annie Avakian, Natwar Agrawal and Ranga Vemuri. Reconfigurable Multicore Architecture for Dynamic Processor Reallocation

    Stewart Denholm, Kuen Hung Tsoi and Wayne Luk. Efficient Multi-Node Communication for FPGA Clusters

    Ehsan Zadkhosh, Sepide Fatahi and Mahmood Ahmadi. Performance Analysis of Reconfigurable Processors Using MVA Analysis

    Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang and Jinian Bian. PDPR: Fine-grained Placement for Dynamic Partially Reconfigurable FPGAs

    Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt. A Connection Router for the Dynamic Reconfiguration of FPGAs

    Hongbing Fan, Yu-Liang Wu and Yue-Ang Chen. R-NoC: an Efficient Packet-Switched Reconfigurable Networks-on-Chip

    Kashif Latif, M Muzaffar Rao, Athar Mahboob and Arshad Aziz. Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms

    Chao Wang, Xi Li, Xuehai Zhou and Xiaojing Feng. CRAIS: A Crossbar based Adaptive Interconnection Scheme

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