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IEEE THAILAND SECTION


IEEE CAS Society
THAILAND Chapter


Mahanakorn University of Technology, THAILAND


National Electronics and Computer Technology Center, Thailand


Xilinx


Celoxica


Altera


Synplicity

 


2006 IEEE International Conference on
Field Programmable Technology
December 13-15, 2006 Bangkok Thailand.



Conference Program

 

Presenter Information (click)

Day1: Wednesday 13 December 2006

8:00am - 8:30am

Coffee & late registration

8:30am - 8:45am

Welcome Address

8:45am - 9:45am

Keynote 1: (Chair: Peter Cheung, Imperial College London )

Closing the Gap between FPGAs and ASICs

Prof. Jonathan Rose, Toronto University

9:45am - 10:00am Coffee

10:00am - 11:30am

Session I: Architechture (Chair: Weng-Fai Wong, National University of Singapore)

ENHANCING THE AREA-EFFICIENCY OF FPGAS WITH HARD CIRCUITS USING SHADOW CLUSTERS
Peter Jamieson and Jonathan Rose

GRANULARITY ASPECTS FOR THE DESIGN OF MULTI-LEVEL RECONFIGURABLE ARCHITECTURES
Sebastian Lange and Martin Middendorf

EVALUATION OF GRANULARITY ON THRESHOLD VOLTAGE CONTROL IN FLEX POWER FPGA
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa and Hanpei Koike

11:30am - 12:00pm

Poster Session I & Coffee

 

12pm - 1:30pm
Lunch
1:30pm - 3:30pm

Session 2: Applications I (Chair: Philip Leong, Chinese University of Hong Kong )

ROBUST AND REAL-TIME AUTOMATIC TARGET RECOGNITION USING PARTIAL HAUSDORFF DISTANCE MEASURE ON RECONFIGURABLE HARDWARE
Jinbo Xu and Yong Dou

INVERSION-BASED HARDWARE GAUSSIAN RANDOM NUMBER GENERATOR: A CASE STUDY OF FUNCTION EVALUATION VIA HIERARCHICAL SEGMENTATION
Dong-U Lee, Ray Cheung, John Villasenor and Wayne Luk

SEED-BASED GENOMIC SEQUENCE COMPARISON USING A FPGA/FLASH ACCELERATOR
Dominique Lavenier, Xinchun Liu and Gilles Georges

AN FPGA IMPLEMENTATION OF THE SIMPLEX ALGORITHM
Samuel Bayliss, Christos-Savvas Bouganis, George Constantinides and Wayne Luk

3:30pm - 4:15pm

Poster Session II & Coffee

 

4:15pm - 5:45pm

Session 3: Tools I (Chair: Guy Lemieux, University of British Columbia)

ON-LINE SCHEDULING OF REAL-TIME TASKS FOR RECONFIGURABLE COMPUTING SYSTEM
Xue-Gong Zhou, Ying Wang, Xun-Zhang Huang and Cheng-Lian Peng

EFFICIENT ALGORITHM FOR FUNCTIONAL SCHEDULING IN HARDWARE/SOFTWARE CO-DESIGN
Jigang Wu, Thambipillai Srikanthan and Tao Jiao

GENERATING HARDWARE FROM OPENMP PROGRAMS
Y. Y. Leow, C. Y. Ng and W. F. Wong

7.00pm-9.00pm

Welcome Reception @ 12th Floor Grand Mercure Fortune Hotel (Open air)

 

 

Day2: Thursday 14 December 2006

8:15am - 8:45am Coffee & late registration
8:45am - 9:45am

Keynote 2: (Chair: Manfred Glesner, T.U. Darmstadt)

Applications of programmable logic in modern particle physics experiments
Prof. Geoff Hall, Imperial College London

9:45am - 10:00am Coffee
10:00am - 12:00pm

Session 4: Architectures II (Chair: Jonathan Rose, University of Toronto)

RECONFIGURABLE FLUX NETWORKS
Stamatis Vassiliadis and Ioannis Sourdis

INTERCONNECT DRIVER DESIGN FOR LONG WIRES IN FIELD-PROGRAMMABLE GATE ARRAYS
Edmund Lee, Guy Lemieux and Shahriar Mirabbasi

WITHIN-DIE DELAY VARIABILITY IN 90NM FPGAS AND BEYOND
Pete Sedcole and Peter Y. K. Cheung

A HIGHLY PARAMETERIZABLE PARALLEL PROCESSOR ARRAY ARCHITECTURE
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov and Juergen Teich

12:00pm - 1:30pm Lunch
1:30pm - 3:30pm

Session 5: Applications II (Chair: Masahiro Fujita, University of Tokyo)

OPTIMIZING THE CRITICAL LOOP IN THE H.264/AVC CABAC DECODER
Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt and Vincent Nollet

REGULAR EXPRESSION MATCHING FOR RECONFIGURABLE PACKET INSPECTION
Joo Bispo, Ioannis Sourdis, Jo ? o M.P. Cardoso and Stamatis Vassiliadis

AUTOMATED DESIGN SPACE EXPLORATION OF FPGA-BASED FFT ARCHITECTURES
Miguel A. Sanchez, Mario Garrido, Marisa Lopez-Vallejo and Carlos Lopez-Barrio

SIGMA-DELTA BASED CLOCK RECOVERY USING ON-CHIP PLL IN FPGA
Ning Ge, Yuyu Liu, Huazhong Yang and Hui Wang

3:30pm - 4:15pm

Poster Session III & Coffee

 

4:15pm - 5:45pm

Session 6: Memory (Chair: Nikil Dutt, UC Irvine)

A HARDWARE CACHE-LINE MEMCPY ACCELERATOR
Stephan Wong, Filipa Duarte and Stamatis Vassiliadis

A NOVEL MEMORY ARCHITECTURE FOR ELLIPTIC CURVE CRYPTOGRAPHY WITH PARALLEL MODULAR MULTIPLIERS
Ralf Laue and Sorin Huss

EMORY SUPPORT DESIGN FOR LU DECOMPOSITION ON THE STARBRIDGE HYPERCOMPUTER
Seth Young, Aravind Dasu, Arvind Sudarsanam and Thomas Hauser

6.00am - 11.00pm

EVENING BANQUET at Siam Niramit

 

 

Day3: Friday 15 December 2006

8:30am - 9:00am Coffee & late registration
9:00am - 10:30am

Session 7: Applications III (Chair: David Kearney, University of South Australia)

FPGA-BASED MSB-FIRST BIT-SERIAL VARIABLE BLOCK SIZE MOTION ESTIMATION PROCESSOR
Brian Li and Philip Leong

FPGA ACCELERATED TATE PAIRING BASED CRYPTOSYSTEMS OVER BINARY FIELDS
Chang Shu, Soonhak Kwon and Kris Gaj

A COMPARISON OF 2-D DISCRETE WAVELET TRANSFORM COMPUTATION SCHEDULES ON FPGAS
Maria Angelopoulou, Konstantinos Masselos, Peter Cheung and Yiannis Andreopoulos

10:30am - 11:00am Coffee
11:00am - 12:30pm

Session 8: Tools II (Chair: Oliver Diessel, University of New South Wales, Asia)

A SEMI-SYNTHETIC CIRCUIT GENERATION TECHNIQUE FOR TESTING INCREMENTAL PLACEMENT AND INCREMENTAL ROUTING TOOLS
David Grant and Guy Lemieux

MULTITHREADED VIRTUAL-MEMORY-ENABLED RECONFIGURABLE HARDWARE ACCELERATORS
Miljan Vuletic, Paolo Ienne, Christopher Claus and Walter Stechele

PGA CORE WATERMARKING BASED ON POWER SIGNATURE ANALYSIS
Daniel Ziener and Juergen Teich

12:30pm - 2:00pm Lunch
2:00pm - 2:30pm

Poster Session IV & Coffee

 

2:30pm - 4:00pm

Session 9: Applications IV (Chair: Christos Bouganis, Imperial College London)

FPGA ACCELERATION OF THE TATE PAIRING IN CHARACTERISTIC 2
Robert Ronan, Colm O hEigeartaigh, Colin Murphy, Michael Scott and Tim Kerins

FADES: A FAULT EMULATION TOOL FOR FAST DEPENDABILITY ASSESSMENT
David de Andres, Juan Carlos Ruiz, Daniel Gil and Pedro Gil

AN ADPATIVE FREQUENCY CONTROL METHOD USING THERMAL FEEDBACK FOR RECONFIGURABLE HARDWARE APPLICATIONS
Phillip Jones, Young Cho and John Lockwood

4:00pm - 4:15pm

Conference close

 

 

 


Poster Session I

FPGA IMPLEMENTATION OF A FUZZY CONTROLLER FOR AUTOMOBILE DC-DC CONVERTERS
Jacobo Alvarez, Alfonso Lago, Andres Nogueiras, Carlos Martinez-Pe ? alver, Jorge Marcos, Jesus Doval and Oscar Lopez

AN ADAPTIVE AND PREDICTIVE ARCHITECTURE FOR PARAMETERISED PIV ALGORITHMS
Nathalie Bochard, Alain Aubert and Virginie Fresse

A NEW REAL TIME PROGRAMMABLE ENCODER FOR LOW DENSITY PARITY CHECK CODE TARGETING A RECONFIGURABLE INSTRUCTION CELL ARCHITECTURE
Zahid Khan and Tughrul Arslan

TIME-SENSITIVE CONTROL-FLOW CHECKING MONITORING FOR MULTITASK SOCS
Fabian Vargas, Leonardo Picolli, Antonio A. de Alecrim Jr., Marlon
Moraes and M ? rcio Gama

ACTIVITY-BASED POWER ESTIMATION AND CHARACTERIZATION OF DSP AND MULTIPLIER BLOCKS IN FPGAS
Nathalie Chan King Choy and Steven J. E. Wilton

IMPLEMENTATION OF A REAL-TIME MULTIPLE INPUT MULTIPLE OUTPUT CHANNEL ESTIMATOR ON THE SMART ANTENNA SOFTWARE RADIO TEST SYSTEM PLATFORM USING THE XILINX VIRTEX 2 PRO FIELD PROGRAMMABLE GATE ARRAY
Peter John Green and Desmond P Taylor

EFFICIENT MANAGEMENT OF CUSTOM INSTRUCTIONS FOR RUN-TIME RECONFIGURABLE INSTRUCTION SET PROCESSORS
Siew-Kei Lam, Bharathi N. Krishnan and Thambipillai Srikanthan

FPGA IMPLEMENTATION FOR AN IRIS BIOMETRIC PROCESSOR
Judith Liu-Jimenez, Raul Sanchez-Reillo, Almudena Lindoso and Oscar Miguel-Hurtado

FPGA IMPLEMENTATION OF TABU SEARCH FOR THE QUADRATIC ASSIGNMENT PROBLEM
Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama


 

Poster Session II

MINIMIZING PEAK POWER FOR APPLICATION CHAINS ON ARCHITECTURES WITH PARTIAL DYNAMIC RECONFIGURATION
Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera and Nikil Dutt

HARDWARE JOIN JAVA: A UNIFIED HARDWARE/SOFTWARE LANGUAGE FOR DYNAMIC PARTIAL RUN TIME RECONFIGURABLE COMPUTING APPLICATIONS
David Kearney and John Hopf

AN FPGA BASED GENERIC PROTOTYPING PLATFORM EMPLOYED IN A CMOS LASER DOPPLER BLOOD FLOW CAMERA
Yiqun Zhu, Barrie Hayes-Gill, Steve Morgan and Nguyen Hoang

AN ADAPTIVE VITERBI DECODER ON THE DYNAMICALLY RECONFIGURABLE PROCESSOR
Shohei Abe, Yohei Hasegawa, Takao Toi, Takashi Inuo and Hideharu Amano

POWERBIT - POWER AWARE ARITHMETIC BIT-WIDTH OPTIMIZATION
Altaf Abdul Gaffar, Jonathan A. Clarke and George A. Constantinides

COMBINING HARDWARE RECONFIGURATION AND ADAPTIVE COMPUTATION FOR A NOVEL SOC DESIGN METHODOLOGY
Marco Santambrogio, Vincenzo Rana, Seda Memik and Donatella Sciuto

HARDWARE CHANNEL MODEL FOR ULTRA WIDEBAND SYSTEMS
Wen-Chih Kan and Gerald E. Sobelman

A LEAKAGE AWARE DESIGN METHODOLOGY FOR POWER-GATED PROGRAMMABLE ARCHITECTURES
Narayan Subramanian, Rajarshee Bharadwaj and Dinesh Bhatia

A 'C' COMPILER FOR IMPLEMENTING FPGA BASED BIT-SERIAL DSP SYSTEMS
Dan Cyca and Laurence E. Turner


 

Poster Session III

PERFORMANCE EVALUATIONS OF RECONFIGME
Grant Wigley and David Kearney

POWER ESTIMATION OF A LUT-BASED MPGA
Francisco-Javier Veredas and Hans-Joerg Pfleiderer

AN FPGA-BASED FLOATING-POINT PROCESSOR ARRAY SUPPORTING A HIGH-PRECISION DOT PRODUCT
Fritz Mayer-Lindenberg

COMMUNICATIONS INFRASTRUCTURE GENERATION FOR MODULAR FPGA RECONFIGURATION
Shannon Koh and Oliver Diessel

FUZZY MODULAR MULTIPLICATION ARCHITECTURE AND LOW COMPLEXITY IPR-PROTECTION FOR FPGA TECHNOLOGY
Abdulrahman Hanoun, Wael Adi and Bassel Soudan

OPTIMAL SET OF BODY BIAS VOLTAGES FOR AN FPGA WITH FIELD-PROGRAMMABLE VTH COMPONENTS
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa and Hanpei Koike

THE COST OF DATA DEPENDENCE IN MOTION VECTOR ESTIMATION FOR RECONFIGURABLE PLATFORMS
Su-Shin Ang, George Constantinides, Wayne Luk and Peter Cheung

COMPARING FLOATING-POINT AND LOGARITHMIC NUMBER REPRESENTATIONS FOR RECONFIGURABLE ACCELERATION
Haohuan Fu, Oskar Mencer and Wayne Luk

DYNAMICALLY RECONFIGURABLE PROTOCOL TRANSDUCER
Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu and Masahiro Fujita


 

Poster Session IV

OPTIMAL TEMPORAL PARTITIONING BASED ON SLOWDOWN AND RETIMING
Christian Plessl, Marco Platzner and Lothar Thiele

MODELING OF GLITCH EFFECTS IN FPGA BASED ARITHMETIC CIRCUITS
Altaf Abdul Gaffar, Jonathan A. Clarke and George A. Constantinides

DESIGN AND VALIDATION OF EXECUTION SCHEMES FOR DYNAMICALLY
RECONFIGURABLE ARCHITECTURES
Tobias Oppold, Sven Eisenhardt and Wolfgang Rosenstiel

PERIODIC LICENSING OF FPGA BASED INTELLECTUAL PROPERTY
Kenneth Kent and Nathaniel Couture

A PERFORMANCE-DRIVEN BIPARTITIONING ALGORITHM FOR MULTI-FPGA
IMPLEMENTATION WITH TIME-MULTIPLEXED I/OS
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura and Yoji Kajitani

A STATISTICAL FRAMEWORK FOR DIMENSIONALITY REDUCTION IMPLEMENTATION IN FPGAS
Christos-Savvas Bouganis, Iosifina Pournara and Peter Y.K. Cheung

HARDALIGN: A PARALLEL PAIRWISE ALIGNMENT HARDWARE APPLICATION
Guilherme Luiz Moritz, Heitor Silverio Lopes and Carlos Raimundo Erig Lima

DECOY CIRCUITS FOR FPGA DESIGN PROTECTION
Bradley Christiansen, Yong Kim, Robert Bennington and Christopher Ristich

HARDWARE ARCHITECTURES FOR MONTE-CARLO BASED FINANCIAL SIMULATION
David Thomas, Jacob, Alexis Bower and Wayne Luk

CUSTOMIZABLE FPGA-BASED ARCHITECTURE FOR VIDEO APPLICATIONS IN REAL TIME
Griselda Salda

SUPER FAST HARDWARE STRING MATCHING
Dan Lo