12/11(Tue.) Pre-conference
12:30-15:30 Tutorial 1 Chair: M.Taiji (Riken)
High-Performance Reconfigurable ComputingTarek El-Ghazawi (George Washington Univ.)
coffee break
15:45-17:45 Tutorial 2 Chair: H.Amano (Keio Univ.)
Dynamically reconfigurable processors in Japan1. A dynamically reconfigurable architecture for stream processing
Takashi Yoshikawa (Toshiba Corporation)
2. Trade off considerations of the DAPDNA devices over
the last 5 years and a look into their future.
Tomoyoshi Sato (IPFlex Inc.)
3.FE-GA: A Dynamically Reconfigurable Processor with High
Performance and Low Power Consumption
Makoto Satoh (Hitachi, Ltd.)
4.Reconfigurable Architecture for Car Tuners
Makoto Ozone (SANYO Electric Co., Ltd.)
5.MX1: Multi matrix-processor core architecture and
real-time image processing application
Katsuya Mizumoto (Renesas Technology Corp.)
18:00 Reception
12/12(Wed.) 1st day
8:30-8:45 Welcome Address: T.Nakamura (Tohoku Univ.)
8:45-9:45 Key note Chair: H.Yasuura (Kyushu Univ.)
Power and the Future FPGA ArchitecturesSinan Kaptanoglu (Actel Corporation)
9:45-10:45 Poster 1 & Coffee
10:45-12:15 Session 1: Tools I Chair: W.-K. Mak (National Tsing Hua Univ.)
Memory Footprint Reduction For FPGA Routing AlgorithmsScott Chin and Steve Wilton
SOC implementation of wave-pipelined circuits
Seetharaman Gopalakrishnan and Venkataramani Balasubramanian
Self-characterization of Combinatorial Circuit Delays in FPGAs
Justin S. J. Wong, Pete Sedcole and Peter Y. K. Cheung
12:15-13:15 Lunch
13:15-15:15 Session 2: Applications I Chair: P.Leong (Chinese Univ. of Hong Kong)
FPGA Cluster Computing in the ETA Radio TelescopeCameron Patterson, Brian Martin, Steve Ellingson,
John Simonetti and Sean Cutchin
FPGA-based Accelerator Design for RankBoost in Web Search Engines
Ning-Yi XU, Xiong-Fei CAI, Rui GAO, Lei ZHANG and Feng-Hsiung HSU
Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating
System Abstractions
Xin Xie, John Williams and Neil Bergmann
Design and Implementation of an FPGA Architecture for High-Speed Network Feature
Extraction
Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok Choudhary and Joseph Zambreno
15:15-16:15 Poster 2 & Coffee
16:15-18:15 Session 3: Architecture Chair: P.Cheung (Imperial College London)
Architecting Hard Crossbars on FPGAs and Increasing their Area-Efficiency with Shadow ClustersPeter Jamieson and Jonathan Rose
A Method and FPGA Architecture for Real-Time Polymorphic Reconfiguration
Jason Paul, Samuel Stone Yong Kim and Robert Bennington
Reconfigurable Functional Units for Scientific Superscalar Processors
Jonathan Evans, Kyle Rupnow and Katherine Compton
A COARSE GRAINED RECONFIGURABLE ARCHITECTURE FOR VARIABLE BLOCK SIZE MOTION ESTIMATION
Ruchika Verma and Ali Akoglu
12/13(Thu.) 2nd day
8:45-9:30 Invited Speech Chair: M.Fujita (Univ. of Tokyo)
GAPE-DR Project: a combination of peta-scale computing and high-speed networkingKei Hiraki (Univ. of Tokyo)
9:30-10:30 Poster 3 & Coffee
10:30-12:30 Session 4: Tools II O.Diessel (Univ. of New South Wales)
Instrumented Multi-Stage Word-Length OptimizationWilliam Osborne, Jose Coutinho, Ray Cheung, Wayne Luk and Oskar Mencer
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations
David Barrie Thomas and Wayne Luk
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph
Extraction
Alastair Smith, George Constantinides and Peter Cheung
Unifying FPGA Hardware Development
Jacob Alexis Bower, Wei Ning Cho and Wayne Luk
12:30-13:30 Lunch
13:30-15:30 Session 5: Applications II J.Rose (Univ. of Toronto)
Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPSTran Ngoc Thinh, Surin Kittitornkun and Shigenori Tomiyama
HIGH PERFORMANCE HARDWARE IMPLEMENTATION OF SPIKEPROP LEARNING: POTENTIAL AND TRADEOFFS
Marco Aurelio Nuno-Maganda, Miguel Arias-Estrada and Cesar Torres-Huitzil
The Image Forest Transform Architecture
F.A Nabio Augusto Cappabianco, Guido Ara Nzjo and Alexandre Falc Nco
A HIGHLY PARALLEL FPGA BASED IEEE-754 COMPLIANT DOUBLE-PRECISION BINARY FLOATING-POINT
MULTIPLICATION ALGORITHM
Sandeep Venishetti and Ali Akoglu
*15:30-16:30 Poster 4 & Coffee
16:30-18:00 Session 6: Memory & IP Protection G.Constantinides (Imperial College London)
TAS-MRAM based Non-volatile FPGA logic circuitWeisheng ZHAO, Eric BELHAIRE, Bernard DIENY, Guillaume PRENAT and Claude CHAPPERT
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories
Dirk Koch, Christian Beckhoff and Juergen Teich
Dynamic Intellectual Property Protection for Reconfigurable Devices
Tim G.A Nlneysu, Bodo M Nvller and Christof Paar
Banquet
12/14(Fri.) 3rd day
8:45-10:15 Special Session:
What is Exciting about FPT ?Moderator: Wayne Luk (Imperial College London)
Peter Cheung (Imerial College London)
Brent Nelson (Brigham Young Univ.)
Jonathan Rose (Univ. of Tronto)
Philip Leong (Chinese University of Hong Kong)
10:15-10:30 Coffee break
10:30-12:30 Session 7: Applications III T.Hironaka (Hiroshima City Univ.)
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle PhysicsMing Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez and
Zhenan Liu
Efficient and High-Throughput Implementations of AES-GCM on FPGAs
Gang Zhou, Harald Michalik and Lasloz Hinsenkamp
A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA
Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi,
Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano and Hideharu Amano
An Approach for Applying Large Filters on Large Images using FPGA
Shingo Kawada and Tsutomu Maruyama
12:30-13:20 Lunch
13:20-14:50 Session 8: Tools III S.Kimura (Waseda Univ.)
Run-Time Management of Reconfigurable Hardware Tasks using Embedded LinuxKrzysztof Kobsciuszkiewicz, Fearghal Morgan and Krzysztof Kepa
Implementations of Reconfigurable Logic Arrays on FPGAs
Tsutomu Sasao and Hiroki Nakahara
Net Length Based Routability Driven Packing
Audip Pandit and Ali Akoglu
14:50-15:00 Closing
Poster session details
Poster Session IP1-1: FPGA-based Streaming Computation for Lattice Boltzmann Method
Kentaro Sano, Oliver Pell, Wayne Luk and Satoru Yamamoto
P1-2: Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures
Kai-Jung Shih, Chin-Chieh Hung, and Pao-Ann Hsiung
P1-3: An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture
Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida and Toshinori Sueyoshi
P1-4: Improving bounds for FPGA Logic Minimization
Tim Todman, Haohan Fu, Oskar Mencer and Wayne Luk
P1-5: Floating-Point Matrix Multiplication in a Polymorphic Processor
Georgi K. Kuzmanov and Wouter M. van Oijen
P1-6: A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware
Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane and Kenji Toda
P1-7: Productivity Of High-Level Languages On Reconfigurable Computers: An HPC Perspective
Esam El-Araby, Preetham Nosum and Tarek El-Ghazawi
P1-8: A Systolic Agorithm for the Quadratic Assignment Problem and its FPGA Implementation
Yoshihiro Kimura, Shin'ichi Wakabayashi and Shinobu Nagayama
P1-9: Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture
Daisaku Seto and Minoru Watanabe
Poster Session II
P2-1: Efficient Mesh of Tree Interconnect for FPGA Architecture
ZIED MARRAKCHI, HAYDER MRABET, CHRISTIAN MASSON and HABIB MEHREZ
P2-2: Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays
Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura and Hideharu Amano
P2-3: AN FPGA Based Traveling-Wave Fault Location System
David P Coggins, David W P Thomas, Barrie R Hayes-Gill and Yiqun Zhu
P2-4: NICFlex: A Functional Verification Accelerator for An RTL NIC Design
Xianyang Jiang, Xiaomin Li, Yue Tian and Kai Wang
P2-5: Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip
Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa and Hanpei Koike
P2-6: Optimal Buffering of FPGA Interconnect for Expected Delay optimization
Yi-Ru He and Wai-Kei Mak
P2-7: FPGA-Based 3-D engine for high-speed 3-D measurement based on light section method
Yachide Yusuke, Makoto Ikeda and Kunihiro Asada
P2-8: A 62.5 ns holographic reconfiguration for an optically differential reconfigurable gate array
Mao Nakajima and Minoru Watanabe
P2-9: Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems
Zubair Nawaz, Ozana Silvia Dragomir, Thomas Marconi, Elena Moscu Panainte, Koen Bertels and Stamatis Vassiliadis
Poster Session III
P3-1: A Rapid Prototyping of Real-Time Pattern Generator for Step-and-Scan Lithography Using Digital Micromirror Device
Naoto Miyamoto, Masahiko Shimakage, Tatsuo Morimoto, Kazuya Kadota, Shigetoshi Sugawa and Tadahiro Ohmi
P3-2: High Performance Software-Hardware Network Intrusion Detection System
Ryan Proudfoot, Kenneth B. Kent, Eric Aubanel and Nan Chen
P3-3: A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks
Heiko Hinkelmann, Peter Zipf and Manfred Glesner
P3-4: FPGA implementation of a statically reconfigurable Java environment for embedded systems
Shinsuke Nino, Takayuki Mori, YoungHun Ko, Yuichiro Shibata and Kiyoshi Oguri
P3-5: A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing
Nao Iwata, Shingo Kagami and Koichi Hashimoto
P3-6: A BALANCED VECTOR-QUANTIZATION PROCESSOR ELIMINATING REDUNDANT CALCULATION FOR REAL-TIME MOTION PICTURE COMPRESSION
Masahiro Konda, Takahiro Nakayama, Naoto Miyamoto and Tadahiro Ohmi
P3-7: Real-time Segmentation of Color Images based on K-Means Clustering on FPGA
Takashi Saegusa and Tsutomu Maruyama
P3-8: A PORTABLE MEMORY ACCESS FRAMEWORK FOR HIGH-PERFORMANCE RECONFIGURABLE COMPUTERS
Miaoqing Huang, Ivan Gonzalez and Tarek El-Ghazawi
P3-9: The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex Multiple Input Multiple Output Instruction-Set Extensions
Carlo Galuzzi, Koen Bertels and Stamatis Vassiliadis
P3-10: A Case for Soft Vector Processors in FPGAs
Jason Yu and Guy Lemieux
P3-11: A Portable Co-Verification System Which Generates Transactor and Testbench Automatically
Takahito Nakajima, Shigeru Namiki, Shuhei Kinoshita and Naohiko Shimizu
Poster Session IV
P4-1: Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation
William Kamp and Andrew Bainbridge-Smith
P4-2: A Novel Network Architecture Support for Fast Reconfiguration
Jenny Yi-Chun Kuo, Hossam El Gindy and Anderson Kuei-An Ku
P4-3: A Mapping method for Multi-processing Execution on Dynamically Reconfigurable Processors
Vu Manh Tuan, Yohei Hasegawa and Hideharu Amano
P4-4: A Programmable Load/Store Unit on C-based Hardware Design for FPGA
Akira Yamawaki and Masahiko Iwane
P4-5: An efficient FPGA-based implementation of Pollard's (
-1) factorization algorithmDimitrios Meintanis and Ioannis Papaefstathiou
P4-6: A NOVEL ASYNCHRONOUS E-FPGA ARCHITECTURE FOR SECURITY APPLICATIONS
Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst and Jean-luc Danger
P4-7: A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA
James Dykes, Paulman Chan, Glenn Chapman and Lesley Shannon
P4-8: Compound Uniform Random Number Generators with On-Chip Correlation and Distribution Measurements
Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce Cockburn and Christian Schlegel
P4-9: Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
Thomas Schweizer, Tobias Oppold, Julio Filho, Sven Eisenhardt, Kai Blocher and Wolfgang Rosenstiel